@@ -13,7 +13,11 @@ struct law_entry law_table[] = {
#ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
+#ifdef CONFIG_TARGET_P1020RDB_PD
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#else
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
+#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
#endif
@@ -39,9 +39,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
+#ifdef CONFIG_TARGET_P1020RDB_PD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_64M, 1),
+#else
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_16M, 1),
+#endif
#ifdef CONFIG_PCI
/* *I*G* - PCI memory 1.5G */
@@ -243,10 +243,17 @@
#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
| BR_PS_16 | BR_V)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_FLASH_OR_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | \
OR_GPCM_SCY_15 | OR_GPCM_TRLX | \
OR_GPCM_EHTR | OR_GPCM_EAD)
+#else
+#define CONFIG_FLASH_OR_PRELIM (OR_AM_16MB | OR_GPCM_CSNT | \
+ OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | \
+ OR_GPCM_SCY_15 | OR_GPCM_TRLX | \
+ OR_GPCM_EHTR | OR_GPCM_EAD)
+#endif
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
FLASH NOR on P1020RDB-PD has size of 64 MB. On all other P1/P2 RDB boards it has only size of 16 MB. So fix this size in TLB, LAW and LBC OR registers. Signed-off-by: Pali Rohár <pali@kernel.org> --- board/freescale/p1_p2_rdb_pc/law.c | 4 ++++ board/freescale/p1_p2_rdb_pc/tlb.c | 6 ++++++ include/configs/p1_p2_rdb_pc.h | 7 +++++++ 3 files changed, 17 insertions(+)