@@ -9,7 +9,6 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
#ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
@@ -65,9 +65,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_64K, 1),
#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE
@@ -247,7 +247,6 @@
* 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
* (early boot only)
* 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
- * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
* 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
@@ -359,14 +358,6 @@
BR_PS_8 | BR_V)
#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
-#define CONFIG_SYS_PMC_BASE 0xff980000
-#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
-#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
- BR_PS_8 | BR_V)
-#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
- OR_GPCM_EAD)
-
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define __VSCFW_ADDR "vscfw_addr=ef000000\0"
@@ -637,8 +637,6 @@ CONFIG_PHY_RESET_DELAY
CONFIG_PL011_CLOCK
CONFIG_PL01x_PORTS
CONFIG_PM
-CONFIG_PMC_BR_PRELIM
-CONFIG_PMC_OR_PRELIM
CONFIG_PME_PLAT_CLK_DIV
CONFIG_PMU
CONFIG_PMW_BASE
@@ -1796,8 +1794,6 @@ CONFIG_SYS_PLL_FDR
CONFIG_SYS_PLL_ODR
CONFIG_SYS_PLL_SETTLING_TIME
CONFIG_SYS_PMAN
-CONFIG_SYS_PMC_BASE
-CONFIG_SYS_PMC_BASE_PHYS
CONFIG_SYS_PME_CLK
CONFIG_SYS_POST_MEMORY
CONFIG_SYS_POST_MEM_REGIONS
From whole P1/P2 family of RDB boards is TDM-PMC card (PCI Mezzanine Card, Freescale PQ-MDS-T1) available only on P1021RDB and P1025RDB boards. So address mapping for TDM-PMC card on LBC should not be enabled on any other P1/P2 RDB board as there is no device at that TDM-PMC address. Support for P1021RDB and P1025RDB boards was already removed from mainline U-Boot in commits 6d1dd76afe85 ("board/freescale: Remove P1021RDB board support") and d521cece5adb ("board/freescale: Remove P1025RDB board support"). So do not enable TDM-PMC address mapping on remaining P1/P2 RDB boards and remove all macros related to TDM-PMC address mappings. Signed-off-by: Pali Rohár <pali@kernel.org> --- board/freescale/p1_p2_rdb_pc/law.c | 1 - board/freescale/p1_p2_rdb_pc/tlb.c | 3 --- include/configs/p1_p2_rdb_pc.h | 9 --------- scripts/config_whitelist.txt | 4 ---- 4 files changed, 17 deletions(-)