| Message ID | 20220411162634.69647-7-ovpanait@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Michal Simek |
| Headers | show |
| Series | [01/10] microblaze: start.S: remove unused code | expand |
On 4/11/22 18:26, Ovidiu Panait wrote: > All flush_cache() calls in microblaze code are supposed to flush the > entire instruction and data caches, so introduce flush_cache_all() > helper to handle this. > > Also, provide implementations for flush_dcache_all() and > invalidate_icache_all() so that icache and dcache u-boot commands can > work. > > Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> > --- > > arch/microblaze/cpu/cache.c | 20 ++++++++++++++++++-- > arch/microblaze/cpu/start.S | 8 ++------ > arch/microblaze/include/asm/cache.h | 5 +++++ > arch/microblaze/lib/bootm.c | 2 +- > 4 files changed, 26 insertions(+), 9 deletions(-) > > diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c > index 2814c1dc07..60b6d549d7 100644 > --- a/arch/microblaze/cpu/cache.c > +++ b/arch/microblaze/cpu/cache.c > @@ -24,6 +24,11 @@ static void __invalidate_icache(ulong addr, ulong size) > } > } > > +void invalidate_icache_all(void) > +{ > + __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE); > +} > + > static void __flush_dcache(ulong addr, ulong size) > { > if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) { > @@ -38,6 +43,11 @@ static void __flush_dcache(ulong addr, ulong size) > } > } > > +void flush_dcache_all(void) > +{ > + __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE); > +} > + > int dcache_status(void) > { > int i = 0; > @@ -65,7 +75,7 @@ void icache_enable(void) > > void icache_disable(void) > { > - __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE); > + invalidate_icache_all(); > > MSRCLR(0x20); > } > @@ -77,7 +87,7 @@ void dcache_enable(void) > > void dcache_disable(void) > { > - __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE); > + flush_dcache_all(); > > MSRCLR(0x80); > } > @@ -87,3 +97,9 @@ void flush_cache(ulong addr, ulong size) > __invalidate_icache(addr, size); > __flush_dcache(addr, size); > } > + > +void flush_cache_all(void) > +{ > + invalidate_icache_all(); > + flush_dcache_all(); > +} > diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S > index 94984148de..7f7b5f5cb5 100644 > --- a/arch/microblaze/cpu/start.S > +++ b/arch/microblaze/cpu/start.S > @@ -52,9 +52,7 @@ _start: > #endif > > /* Flush cache before enable cache */ > - addik r5, r0, 0 > - addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE > - bralid r15, flush_cache > + bralid r15, flush_cache_all > nop > > /* enable instruction and data cache */ > @@ -283,9 +281,7 @@ relocate_code: > addk r20, r20, r23 > > /* Flush caches to ensure consistency */ > - addik r5, r0, 0 > - addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE > - bralid r15, flush_cache > + bralid r15, flush_cache_all > nop > > 2: addi r5, r31, 0 /* gd is initialized in board_r.c */ > diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h > index baee01a0e2..c39b66dd7d 100644 > --- a/arch/microblaze/include/asm/cache.h > +++ b/arch/microblaze/include/asm/cache.h > @@ -18,4 +18,9 @@ > #define ARCH_DMA_MINALIGN 16 > #endif > > +/** > + * flush_cache_all - flush the entire instruction/data caches > + */ > +void flush_cache_all(void); > + > #endif /* __MICROBLAZE_CACHE_H__ */ > diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c > index 59b757c857..af946b8642 100644 > --- a/arch/microblaze/lib/bootm.c > +++ b/arch/microblaze/lib/bootm.c > @@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) > "(fake run for tracing)" : ""); > bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); > > - flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE); > + flush_cache_all(); > > if (!fake) { > /* This looks good. M
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index 2814c1dc07..60b6d549d7 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -24,6 +24,11 @@ static void __invalidate_icache(ulong addr, ulong size) } } +void invalidate_icache_all(void) +{ + __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE); +} + static void __flush_dcache(ulong addr, ulong size) { if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) { @@ -38,6 +43,11 @@ static void __flush_dcache(ulong addr, ulong size) } } +void flush_dcache_all(void) +{ + __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE); +} + int dcache_status(void) { int i = 0; @@ -65,7 +75,7 @@ void icache_enable(void) void icache_disable(void) { - __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE); + invalidate_icache_all(); MSRCLR(0x20); } @@ -77,7 +87,7 @@ void dcache_enable(void) void dcache_disable(void) { - __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE); + flush_dcache_all(); MSRCLR(0x80); } @@ -87,3 +97,9 @@ void flush_cache(ulong addr, ulong size) __invalidate_icache(addr, size); __flush_dcache(addr, size); } + +void flush_cache_all(void) +{ + invalidate_icache_all(); + flush_dcache_all(); +} diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 94984148de..7f7b5f5cb5 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -52,9 +52,7 @@ _start: #endif /* Flush cache before enable cache */ - addik r5, r0, 0 - addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE - bralid r15, flush_cache + bralid r15, flush_cache_all nop /* enable instruction and data cache */ @@ -283,9 +281,7 @@ relocate_code: addk r20, r20, r23 /* Flush caches to ensure consistency */ - addik r5, r0, 0 - addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE - bralid r15, flush_cache + bralid r15, flush_cache_all nop 2: addi r5, r31, 0 /* gd is initialized in board_r.c */ diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h index baee01a0e2..c39b66dd7d 100644 --- a/arch/microblaze/include/asm/cache.h +++ b/arch/microblaze/include/asm/cache.h @@ -18,4 +18,9 @@ #define ARCH_DMA_MINALIGN 16 #endif +/** + * flush_cache_all - flush the entire instruction/data caches + */ +void flush_cache_all(void); + #endif /* __MICROBLAZE_CACHE_H__ */ diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 59b757c857..af946b8642 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) "(fake run for tracing)" : ""); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); - flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE); + flush_cache_all(); if (!fake) { /*
All flush_cache() calls in microblaze code are supposed to flush the entire instruction and data caches, so introduce flush_cache_all() helper to handle this. Also, provide implementations for flush_dcache_all() and invalidate_icache_all() so that icache and dcache u-boot commands can work. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> --- arch/microblaze/cpu/cache.c | 20 ++++++++++++++++++-- arch/microblaze/cpu/start.S | 8 ++------ arch/microblaze/include/asm/cache.h | 5 +++++ arch/microblaze/lib/bootm.c | 2 +- 4 files changed, 26 insertions(+), 9 deletions(-)