From patchwork Fri Apr 8 08:07:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1614770 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KZWDq05wfz9sG6 for ; Fri, 8 Apr 2022 18:11:54 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9051B83DF5; Fri, 8 Apr 2022 10:11:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ziswiler.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 2C9E883DEE; Fri, 8 Apr 2022 10:11:40 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 748E383DB2 for ; Fri, 8 Apr 2022 10:08:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ziswiler.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=marcel@ziswiler.com Received: from toolbox.int.toradex.com ([81.221.85.15]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1N8Won-1o72Bi1SIj-014W30; Fri, 08 Apr 2022 10:07:51 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Cc: Philippe Schenker , Marcel Ziswiler , Fabio Estevam , "NXP i.MX U-Boot Team" , Stefano Babic Subject: [PATCH v1 16/24] board: colibri-imx6ull: fix detecting ethernet phy Date: Fri, 8 Apr 2022 10:07:11 +0200 Message-Id: <20220408080719.342072-17-marcel@ziswiler.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220408080719.342072-1-marcel@ziswiler.com> References: <20220408080719.342072-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:bDFogH3xMGlYWp8vnNEEFzJ1fH2zPiM34k+Z2EVk+meUqxkVSLv VMbdKHCPip2gMIAhYdM2FcBRarjpuoaDUcwjCaA4TTMzoJgBmKX+7y1AclQKlzyjZpyCpOv 7QZNAzz0BcsUpLqSQWGXhatrdDsiBcmc9RVC1ifiwoFYCrZFF1KEpCDGL+OJ2bm+aSafKRA nrrAPr2oulXnwqfTDVsNw== X-UI-Out-Filterresults: notjunk:1;V03:K0:QnHt+IsTObw=:IbPckxf3CB1Up8GyttMtmD eIKI1bcZIMXDxM4XWX1bdWpGh5jyyNRltNpk22vNpmTBpHUVdy5m065RDcebum7iSj+mTKuq4 xaQrzo5fbOYt/XOUdHMstrXNpFkaw/vYVJK7O9daVmO/p/4xCSrvUhbez3tJ9DsIHxMHXc2aE F9kBbZ0degZ3OhYkgz3rf2kC/u8Z6syEldIjUhD8nIcqpcX7XHXEc7oNQ7JGqvASSeRnTblm0 9j4LGGCGIUaafnXHBl5Koa0AtUopy65Kqy+ZjF88aRx+r4l61xXIW3IOUD3rtLO2a6IdGYSDs vpXKQYkebsUq+bahbhIXhXhgmu2teuvJIwMGtfyO0od0drxbX5cJ+Tadc9JdfF+ajHW9kD/TW Gu3OCTguhkJf3nORUnHd96GZwWkleUqDIZgiqdbNtXmv/rp52paeqO0AEM05uHnvs0el1VJGJ dml1q1sV3rMLFZJTCkgHZGipRP/4/saz8X4r2clCzdShc5tjdO2l0L5Nn09k2rAE33r6aJPkp XTPapHBKhPp0ReduRtG8dDp6Qk7t+K3xitnWOl4Oxp05O+UiVzyAjGfG82wvEmAlUUVcE1s4R JTpTu3uWJtBaZ9sHYQay3Hh/rae/USGzFEDl5/13nbyYJF7fDUOE2jB2QZpLZsHaxrgQH2Rus o6SAK+GWoOVJK93KWXK5ib0ko31waUodC+hctG0USnpbI45zXJSv2pSdqAtX4extRM73GXoUx joM1d8R+eqRXyDIu X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Philippe Schenker Now that it is possible to use regulator-fixed-clock make use of it. This makes U-Boot detect the PHY on first cold-boot. This commit also adjusts the code in setup_fec and follows how it is done in mx6ullevk.c This commit also slows down the boot-process by about 150ms as it now waits for the regulator-fixed-clock voltage that drives the PHY to go up. If you rely on very fast boot-speeds and don't need ethernet for your boot-process you can safely revert the changes on imx6ull-colibri.dtsi Signed-off-by: Philippe Schenker Signed-off-by: Marcel Ziswiler --- arch/arm/dts/imx6ull-colibri.dtsi | 13 +++++++++++ .../toradex/colibri-imx6ull/colibri-imx6ull.c | 23 +++++++------------ 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/arch/arm/dts/imx6ull-colibri.dtsi b/arch/arm/dts/imx6ull-colibri.dtsi index 1fa9d10412e..cbf037be7eb 100644 --- a/arch/arm/dts/imx6ull-colibri.dtsi +++ b/arch/arm/dts/imx6ull-colibri.dtsi @@ -58,6 +58,18 @@ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */ vin-supply = <®_5v0>; }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed-clock"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "eth_phy"; + regulator-type = "voltage"; + vin-supply = <®_module_3v3>; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + startup-delay-us = <150000>; + }; }; &adc1 { @@ -78,6 +90,7 @@ pinctrl-0 = <&pinctrl_enet2>; phy-mode = "rmii"; phy-handle = <ðphy1>; + phy-supply = <®_eth_phy>; status = "okay"; mdio { diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index 3244184f272..ba4e0df2c27 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -100,28 +100,21 @@ static int setup_fec(void) struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; - /* provide the PHY clock from the i.MX 6 */ + /* + * Use 50MHz anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + ret = enable_fec_anatop_clock(1, ENET_50MHZ); if (ret) return ret; - /* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */ - clrsetbits_le32(&iomuxc_regs->gpr[1], - IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, - IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); - - /* give new Ethernet PHY power save mode circuitry time to settle */ - mdelay(300); + enable_enet_clk(1); return 0; } - -int board_phy_config(struct phy_device *phydev) -{ - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; -} #endif /* CONFIG_FEC_MXC */ int board_init(void)