| Message ID | 20220125152646.3780-13-a-govindraju@ti.com |
|---|---|
| State | Accepted |
| Commit | 4f260bbeeb3b53e7c4045db90f6516e1c6d5338d |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | J721S2: Add initial support | expand |
On Tue, Jan 25, 2022 at 08:56:38PM +0530, Aswath Govindraju wrote: > There are 4 lanes in the single instance of J721S2 SERDES. Each SERDES > lane mux can select upto 4 different IPs. Define all the possible > functions. > > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> First, this is now applied to u-boot/master. Second, to follow up on some of my previous feedback, there is for example now: https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/options/u-boot.yaml and I expect that this binding, and other relevant "the SoC needs these, but the Linux kernel does not" will be submitted upstream to dt-schema and then synced back to U-Boot (and then yes, we don't _yet_ support the yaml checking in U-Boot natively, but, that's something else to solve). Thanks!
diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index d417b9268b16..d3116c52ab72 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -95,4 +95,26 @@ #define AM64_SERDES0_LANE0_PCIE0 0x0 #define AM64_SERDES0_LANE0_USB 0x1 +/* J721S2 */ + +#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 +#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 +#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J721S2_SERDES0_LANE1_USB 0x2 +#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 +#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 +#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J721S2_SERDES0_LANE3_USB 0x2 +#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */
There are 4 lanes in the single instance of J721S2 SERDES. Each SERDES lane mux can select upto 4 different IPs. Define all the possible functions. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> --- include/dt-bindings/mux/ti-serdes.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)