diff --git a/README b/README
index 40ef21df3b5..56c9bc3e676 100644
--- a/README
+++ b/README
@@ -1006,19 +1006,6 @@ The following options need to be configured:
 - Keyboard Support:
 		See Kconfig help for available keyboard drivers.
 
-- Video support:
-		CONFIG_FSL_DIU_FB
-		Enable the Freescale DIU video driver.	Reference boards for
-		SOCs that have a DIU should define this macro to enable DIU
-		support, and should also define these other macros:
-
-			CONFIG_SYS_DIU_ADDR
-
-		The DIU driver will look for the 'video-mode' environment
-		variable, and if defined, enable the DIU as a console during
-		boot.  See the documentation file doc/README.video for a
-		description of this variable.
-
 - LCD Support:	CONFIG_LCD
 
 		Define this to enable LCD support (for output to LCD
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index c8f62bfc198..f13965daf2e 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -44,8 +44,6 @@ ifndef CONFIG_RAMBOOT_PBL
 obj-$(CONFIG_FSL_FIXED_MMC_LOCATION)	+= sdhc_boot.o
 endif
 
-obj-$(CONFIG_FSL_DIU_CH7301)	+= diu_ch7301.o
-
 ifdef CONFIG_ARM
 obj-$(CONFIG_DEEP_SLEEP)		+= arm_sleep.o
 else
diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c
deleted file mode 100644
index 05e6a3acf11..00000000000
--- a/board/freescale/common/diu_ch7301.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
- * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
- *	    Wang Dongsheng <dongsheng.wang@freescale.com>
- *
- * This file is copied and modified from the original t1040qds/diu.c.
- * Encoder can be used in T104x and LSx Platform.
- */
-
-#include <common.h>
-#include <stdio_dev.h>
-#include <i2c.h>
-#include <linux/delay.h>
-
-#define I2C_DVI_INPUT_DATA_FORMAT_REG		0x1F
-#define I2C_DVI_PLL_CHARGE_CNTL_REG		0x33
-#define I2C_DVI_PLL_DIVIDER_REG			0x34
-#define I2C_DVI_PLL_SUPPLY_CNTL_REG		0x35
-#define I2C_DVI_PLL_FILTER_REG			0x36
-#define I2C_DVI_TEST_PATTERN_REG		0x48
-#define I2C_DVI_POWER_MGMT_REG			0x49
-#define I2C_DVI_LOCK_STATE_REG			0x4D
-#define I2C_DVI_SYNC_POLARITY_REG		0x56
-
-/*
- * Set VSYNC/HSYNC to active high. This is polarity of sync signals
- * from DIU->DVI. The DIU default is active igh, so DVI is set to
- * active high.
- */
-#define I2C_DVI_INPUT_DATA_FORMAT_VAL		0x98
-
-#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL	0x06
-#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL	0x26
-#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL	0xA0
-#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL	0x08
-#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL	0x16
-#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL	0x60
-
-/* Clear test pattern */
-#define I2C_DVI_TEST_PATTERN_VAL		0x18
-/* Exit Power-down mode */
-#define I2C_DVI_POWER_MGMT_VAL			0xC0
-
-/* Monitor polarity is handled via DVI Sync Polarity Register */
-#define I2C_DVI_SYNC_POLARITY_VAL		0x00
-
-/* Programming of HDMI Chrontel CH7301 connector */
-int diu_set_dvi_encoder(unsigned int pixclock)
-{
-	int ret;
-	u8 temp;
-
-	temp = I2C_DVI_TEST_PATTERN_VAL;
-#if CONFIG_IS_ENABLED(DM_I2C)
-	struct udevice *dev;
-
-	ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
-				      CONFIG_SYS_I2C_DVI_ADDR,
-				      1, &dev);
-	if (ret) {
-		printf("%s: Cannot find udev for a bus %d\n", __func__,
-		       CONFIG_SYS_I2C_DVI_BUS_NUM);
-		return ret;
-	}
-	ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select proper dvi test pattern\n");
-		return ret;
-	}
-	temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
-	ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi input data format\n");
-		return ret;
-	}
-
-	/* Set Sync polarity register */
-	temp = I2C_DVI_SYNC_POLARITY_VAL;
-	ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi syc polarity\n");
-		return ret;
-	}
-
-	/* Set PLL registers based on pixel clock rate*/
-	if (pixclock > 65000000) {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	} else {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	}
-
-	temp = I2C_DVI_POWER_MGMT_VAL;
-	ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi power mgmt\n");
-		return ret;
-	}
-#else
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
-			&temp, 1);
-	if (ret) {
-		puts("I2C: failed to select proper dvi test pattern\n");
-		return ret;
-	}
-	temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
-			1, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi input data format\n");
-		return ret;
-	}
-
-	/* Set Sync polarity register */
-	temp = I2C_DVI_SYNC_POLARITY_VAL;
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
-			&temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi syc polarity\n");
-		return ret;
-	}
-
-	/* Set PLL registers based on pixel clock rate*/
-	if (pixclock > 65000000) {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_CHARGE_CNTL_REG, 1,	&temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	} else {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	}
-
-	temp = I2C_DVI_POWER_MGMT_VAL;
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
-			&temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi power mgmt\n");
-		return ret;
-	}
-#endif
-
-	udelay(500);
-
-	return 0;
-}
diff --git a/board/freescale/common/diu_ch7301.h b/board/freescale/common/diu_ch7301.h
deleted file mode 100644
index f35661cdc49..00000000000
--- a/board/freescale/common/diu_ch7301.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DIU_HDMI_CH7301__
-#define __DIU_HDMI_CH7301__
-
-/* Programming of HDMI Chrontel CH7301 connector */
-int diu_set_dvi_encoder(unsigned int pixclock);
-
-#endif
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
index d67e9412ecd..a9495019430 100644
--- a/board/freescale/t104xrdb/Makefile
+++ b/board/freescale/t104xrdb/Makefile
@@ -8,7 +8,6 @@ else
 obj-y	+= t104xrdb.o
 obj-y	+= cpld.o
 obj-y	+= eth.o
-obj-$(CONFIG_FSL_DIU_FB)+= diu.o
 endif
 obj-y	+= ddr.o
 obj-y	+= law.o
diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c
deleted file mode 100644
index 022d329713e..00000000000
--- a/board/freescale/t104xrdb/diu.c
+++ /dev/null
@@ -1,83 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
- */
-
-#include <clock_legacy.h>
-#include <asm/io.h>
-#include <common.h>
-#include <command.h>
-#include <fsl_diu_fb.h>
-#include <linux/ctype.h>
-
-#include "../common/diu_ch7301.h"
-
-#include "cpld.h"
-#include "t104xrdb.h"
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register. So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F		0x10000000
-#define AD_ALPHA_C_SHIFT	25
-#define AD_BLUE_C_SHIFT		23
-#define AD_GREEN_C_SHIFT	21
-#define AD_RED_C_SHIFT		19
-#define AD_PIXEL_S_SHIFT	16
-#define AD_COMP_3_SHIFT		12
-#define AD_COMP_2_SHIFT		8
-#define AD_COMP_1_SHIFT		4
-#define AD_COMP_0_SHIFT		0
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
-	unsigned long speed_ccb, temp;
-	u32 pixval;
-	int ret;
-
-	speed_ccb = get_bus_freq(0);
-	temp = 1000000000 / pixclock;
-	temp *= 1000;
-	pixval = speed_ccb / temp;
-
-	/* Program HDMI encoder */
-	ret = diu_set_dvi_encoder(temp);
-	if (ret) {
-		puts("Failed to set DVI encoder\n");
-		return;
-	}
-
-	/* Program pixel clock */
-	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
-		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
-
-	/* enable clock*/
-	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
-		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
-	u32 pixel_format;
-	u8 sw;
-
-	/*Configure Display ouput port as HDMI*/
-	sw = CPLD_READ(sfp_ctl_status);
-	CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
-
-	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
-		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
-		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
-		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
-		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
-	printf("DIU: Switching to monitor DVI @ %ux%u\n",  xres, yres);
-
-	return fsl_diu_init(xres, yres, pixel_format, 0);
-}
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 656b981ca9d..4f8fe3810b3 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -31,7 +31,6 @@ obj-y += ti/
 obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
 obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 obj-$(CONFIG_FORMIKE) += formike.o
-obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
 obj-$(CONFIG_IHS_VIDEO_OUT) += ihs_video_out.o
 obj-$(CONFIG_LD9040) += ld9040.o
 obj-$(CONFIG_LG4573) += lg4573.o
diff --git a/drivers/video/fsl_diu_fb.c b/drivers/video/fsl_diu_fb.c
deleted file mode 100644
index 6e335b5f43d..00000000000
--- a/drivers/video/fsl_diu_fb.c
+++ /dev/null
@@ -1,415 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
- * Authors: York Sun <yorksun@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- *
- * FSL DIU Framebuffer driver
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-
-#include "videomodes.h"
-#include <fsl_diu_fb.h>
-#include <linux/list.h>
-#include <linux/fb.h>
-
-/* This setting is used for the ifm pdm360ng with PRIMEVIEW PM070WL3 */
-static struct fb_videomode fsl_diu_mode_800_480 = {
-	.name		= "800x480-60",
-	.refresh	= 60,
-	.xres		= 800,
-	.yres		= 480,
-	.pixclock	= 31250,
-	.left_margin	= 86,
-	.right_margin	= 42,
-	.upper_margin	= 33,
-	.lower_margin	= 10,
-	.hsync_len	= 128,
-	.vsync_len	= 2,
-	.sync		= 0,
-	.vmode		= FB_VMODE_NONINTERLACED
-};
-
-/* For the SHARP LQ084S3LG01, used on the P1022DS board */
-static struct fb_videomode fsl_diu_mode_800_600 = {
-	.name		= "800x600-60",
-	.refresh	= 60,
-	.xres		= 800,
-	.yres		= 600,
-	.pixclock	= 25000,
-	.left_margin	= 88,
-	.right_margin	= 40,
-	.upper_margin	= 23,
-	.lower_margin	= 1,
-	.hsync_len	= 128,
-	.vsync_len	= 4,
-	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-	.vmode		= FB_VMODE_NONINTERLACED
-};
-
-/*
- * These parameters give default parameters
- * for video output 1024x768,
- * FIXME - change timing to proper amounts
- * hsync 31.5kHz, vsync 60Hz
- */
-static struct fb_videomode fsl_diu_mode_1024_768 = {
-	.name		= "1024x768-60",
-	.refresh	= 60,
-	.xres		= 1024,
-	.yres		= 768,
-	.pixclock	= 15385,
-	.left_margin	= 160,
-	.right_margin	= 24,
-	.upper_margin	= 29,
-	.lower_margin	= 3,
-	.hsync_len	= 136,
-	.vsync_len	= 6,
-	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-	.vmode		= FB_VMODE_NONINTERLACED
-};
-
-static struct fb_videomode fsl_diu_mode_1280_1024 = {
-	.name		= "1280x1024-60",
-	.refresh	= 60,
-	.xres		= 1280,
-	.yres		= 1024,
-	.pixclock	= 9375,
-	.left_margin	= 38,
-	.right_margin	= 128,
-	.upper_margin	= 2,
-	.lower_margin	= 7,
-	.hsync_len	= 216,
-	.vsync_len	= 37,
-	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-	.vmode		= FB_VMODE_NONINTERLACED
-};
-
-static struct fb_videomode fsl_diu_mode_1280_720 = {
-	.name		= "1280x720-60",
-	.refresh	= 60,
-	.xres		= 1280,
-	.yres		= 720,
-	.pixclock	= 13426,
-	.left_margin	= 192,
-	.right_margin	= 64,
-	.upper_margin	= 22,
-	.lower_margin	= 1,
-	.hsync_len	= 136,
-	.vsync_len	= 3,
-	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-	.vmode		= FB_VMODE_NONINTERLACED
-};
-
-static struct fb_videomode fsl_diu_mode_1920_1080 = {
-	.name		= "1920x1080-60",
-	.refresh	= 60,
-	.xres		= 1920,
-	.yres		= 1080,
-	.pixclock	= 5787,
-	.left_margin	= 328,
-	.right_margin	= 120,
-	.upper_margin	= 34,
-	.lower_margin	= 1,
-	.hsync_len	= 208,
-	.vsync_len	= 3,
-	.sync		= FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-	.vmode		= FB_VMODE_NONINTERLACED
-};
-
-/*
- * These are the fields of area descriptor(in DDR memory) for every plane
- */
-struct diu_ad {
-	/* Word 0(32-bit) in DDR memory */
-	__le32 pix_fmt; /* hard coding pixel format */
-	/* Word 1(32-bit) in DDR memory */
-	__le32 addr;
-	/* Word 2(32-bit) in DDR memory */
-	__le32 src_size_g_alpha;
-	/* Word 3(32-bit) in DDR memory */
-	__le32 aoi_size;
-	/* Word 4(32-bit) in DDR memory */
-	__le32 offset_xyi;
-	/* Word 5(32-bit) in DDR memory */
-	__le32 offset_xyd;
-	/* Word 6(32-bit) in DDR memory */
-	__le32 ckmax_r:8;
-	__le32 ckmax_g:8;
-	__le32 ckmax_b:8;
-	__le32 res9:8;
-	/* Word 7(32-bit) in DDR memory */
-	__le32 ckmin_r:8;
-	__le32 ckmin_g:8;
-	__le32 ckmin_b:8;
-	__le32 res10:8;
-	/* Word 8(32-bit) in DDR memory */
-	__le32 next_ad;
-	/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
-	__le32 res[3];
-} __attribute__ ((packed));
-
-/*
- * DIU register map
- */
-struct diu {
-	__be32 desc[3];
-	__be32 gamma;
-	__be32 pallete;
-	__be32 cursor;
-	__be32 curs_pos;
-	__be32 diu_mode;
-	__be32 bgnd;
-	__be32 bgnd_wb;
-	__be32 disp_size;
-	__be32 wb_size;
-	__be32 wb_mem_addr;
-	__be32 hsyn_para;
-	__be32 vsyn_para;
-	__be32 syn_pol;
-	__be32 thresholds;
-	__be32 int_status;
-	__be32 int_mask;
-	__be32 colorbar[8];
-	__be32 filling;
-	__be32 plut;
-} __attribute__ ((packed));
-
-struct diu_addr {
-	void *vaddr;		/* Virtual address */
-	u32 paddr;		/* 32-bit physical address */
-	unsigned int offset;	/* Alignment offset */
-};
-
-static struct fb_info info;
-
-/*
- * Align to 64-bit(8-byte), 32-byte, etc.
- */
-static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
-{
-	u32 offset, ssize;
-	u32 mask;
-
-	ssize = size + bytes_align;
-	buf->vaddr = malloc(ssize);
-	if (!buf->vaddr)
-		return -1;
-
-	memset(buf->vaddr, 0, ssize);
-	mask = bytes_align - 1;
-	offset = (u32)buf->vaddr & mask;
-	if (offset) {
-		buf->offset = bytes_align - offset;
-		buf->vaddr += offset;
-	} else
-		buf->offset = 0;
-
-	buf->paddr = virt_to_phys(buf->vaddr);
-	return 0;
-}
-
-/*
- * Allocate a framebuffer and an Area Descriptor that points to it.  Both
- * are created in the same memory block.  The Area Descriptor is updated to
- * point to the framebuffer memory. Memory is aligned as needed.
- */
-static struct diu_ad *allocate_fb(unsigned int xres, unsigned int yres,
-				  unsigned int depth, char **fb)
-{
-	unsigned long size = xres * yres * depth;
-	struct diu_addr addr;
-	struct diu_ad *ad;
-	size_t ad_size = roundup(sizeof(struct diu_ad), 32);
-
-	/*
-	 * Allocate a memory block that holds the Area Descriptor and the
-	 * frame buffer right behind it.  To keep the code simple, everything
-	 * is aligned on a 32-byte address.
-	 */
-	if (allocate_buf(&addr, ad_size + size, 32) < 0)
-		return NULL;
-
-	ad = addr.vaddr;
-	ad->addr = cpu_to_le32(addr.paddr + ad_size);
-	ad->aoi_size = cpu_to_le32((yres << 16) | xres);
-	ad->src_size_g_alpha = cpu_to_le32((yres << 12) | xres);
-	ad->offset_xyi = 0;
-	ad->offset_xyd = 0;
-
-	if (fb)
-		*fb = addr.vaddr + ad_size;
-
-	return ad;
-}
-
-int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix)
-{
-	struct fb_videomode *fsl_diu_mode_db;
-	struct diu_ad *ad;
-	struct diu *hw = (struct diu *)CONFIG_SYS_DIU_ADDR;
-	u8 *gamma_table_base;
-	unsigned int i, j;
-	struct diu_addr gamma;
-	struct diu_addr cursor;
-
-/* Convert the X,Y resolution pair into a single number */
-#define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
-
-	switch (RESOLUTION(xres, yres)) {
-	case RESOLUTION(800, 480):
-		fsl_diu_mode_db = &fsl_diu_mode_800_480;
-		break;
-	case RESOLUTION(800, 600):
-		fsl_diu_mode_db = &fsl_diu_mode_800_600;
-		break;
-	case RESOLUTION(1024, 768):
-		fsl_diu_mode_db = &fsl_diu_mode_1024_768;
-		break;
-	case RESOLUTION(1280, 1024):
-		fsl_diu_mode_db = &fsl_diu_mode_1280_1024;
-		break;
-	case RESOLUTION(1280, 720):
-		fsl_diu_mode_db = &fsl_diu_mode_1280_720;
-		break;
-	case RESOLUTION(1920, 1080):
-		fsl_diu_mode_db = &fsl_diu_mode_1920_1080;
-		break;
-	default:
-		printf("DIU:   Unsupported resolution %ux%u\n", xres, yres);
-		return -1;
-	}
-
-	/* read mode info */
-	info.var.xres = fsl_diu_mode_db->xres;
-	info.var.yres = fsl_diu_mode_db->yres;
-	info.var.bits_per_pixel = 32;
-	info.var.pixclock = fsl_diu_mode_db->pixclock;
-	info.var.left_margin = fsl_diu_mode_db->left_margin;
-	info.var.right_margin = fsl_diu_mode_db->right_margin;
-	info.var.upper_margin = fsl_diu_mode_db->upper_margin;
-	info.var.lower_margin = fsl_diu_mode_db->lower_margin;
-	info.var.hsync_len = fsl_diu_mode_db->hsync_len;
-	info.var.vsync_len = fsl_diu_mode_db->vsync_len;
-	info.var.sync = fsl_diu_mode_db->sync;
-	info.var.vmode = fsl_diu_mode_db->vmode;
-	info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8;
-
-	/* Memory allocation for framebuffer */
-	info.screen_size =
-		info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
-	ad = allocate_fb(info.var.xres, info.var.yres,
-			 info.var.bits_per_pixel / 8, &info.screen_base);
-	if (!ad) {
-		printf("DIU:   Out of memory\n");
-		return -1;
-	}
-
-	ad->pix_fmt = pixel_format;
-
-	/* Disable chroma keying function */
-	ad->ckmax_r = 0;
-	ad->ckmax_g = 0;
-	ad->ckmax_b = 0;
-
-	ad->ckmin_r = 255;
-	ad->ckmin_g = 255;
-	ad->ckmin_b = 255;
-
-	/* Initialize the gamma table */
-	if (allocate_buf(&gamma, 256 * 3, 32) < 0) {
-		printf("DIU:   Out of memory\n");
-		return -1;
-	}
-	gamma_table_base = gamma.vaddr;
-	for (i = 0; i <= 2; i++)
-		for (j = 0; j < 256; j++)
-			*gamma_table_base++ = j;
-
-	if (gamma_fix == 1) {	/* fix the gamma */
-		gamma_table_base = gamma.vaddr;
-		for (i = 0; i < 256 * 3; i++) {
-			gamma_table_base[i] = (gamma_table_base[i] << 2)
-				| ((gamma_table_base[i] >> 6) & 0x03);
-		}
-	}
-
-	/* Initialize the cursor */
-	if (allocate_buf(&cursor, 32 * 32 * 2, 32) < 0) {
-		printf("DIU:   Can't alloc cursor data\n");
-		return -1;
-	}
-
-	/* Program DIU registers */
-	out_be32(&hw->diu_mode, 0);	/* Temporarily disable the DIU */
-
-	out_be32(&hw->gamma, gamma.paddr);
-	out_be32(&hw->cursor, cursor.paddr);
-	out_be32(&hw->bgnd, 0x007F7F7F);
-	out_be32(&hw->disp_size, info.var.yres << 16 | info.var.xres);
-	out_be32(&hw->hsyn_para, info.var.left_margin << 22 |
-			info.var.hsync_len << 11 |
-			info.var.right_margin);
-
-	out_be32(&hw->vsyn_para, info.var.upper_margin << 22 |
-			info.var.vsync_len << 11 |
-			info.var.lower_margin);
-
-	/* Pixel Clock configuration */
-	diu_set_pixel_clock(info.var.pixclock);
-
-	/* Set the frame buffers */
-	out_be32(&hw->desc[0], virt_to_phys(ad));
-	out_be32(&hw->desc[1], 0);
-	out_be32(&hw->desc[2], 0);
-
-	/* Enable the DIU, set display to all three planes */
-	out_be32(&hw->diu_mode, 1);
-
-	return 0;
-}
-
-void *video_hw_init(void)
-{
-	static GraphicDevice ctfb;
-	const char *options;
-	unsigned int depth = 0, freq = 0;
-
-	if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq,
-				  &options))
-		return NULL;
-
-	/* Find the monitor port, which is a required option */
-	if (!options)
-		return NULL;
-	if (strncmp(options, "monitor=", 8) != 0)
-		return NULL;
-
-	if (platform_diu_init(ctfb.winSizeX, ctfb.winSizeY, options + 8) < 0)
-		return NULL;
-
-	/* fill in Graphic device struct */
-	sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz",
-		ctfb.winSizeX, ctfb.winSizeY, depth, 64, freq);
-
-	ctfb.frameAdrs = (unsigned int)info.screen_base;
-	ctfb.plnSizeX = ctfb.winSizeX;
-	ctfb.plnSizeY = ctfb.winSizeY;
-
-	ctfb.gdfBytesPP = 4;
-	ctfb.gdfIndex = GDF_32BIT_X888RGB;
-
-	ctfb.isaBase = 0;
-	ctfb.pciBase = 0;
-	ctfb.memSize = info.screen_size;
-
-	/* Cursor Start Address */
-	ctfb.dprBase = 0;
-	ctfb.vprBase = 0;
-	ctfb.cprBase = 0;
-
-	return &ctfb;
-}
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 71c96102dd4..aac8103df2b 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -368,18 +368,6 @@
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 
-/* Video */
-#undef CONFIG_FSL_DIU_FB	/* RDB doesn't support DIU */
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-/*
- * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
- * disable empty flash sector detection, which is I/O-intensive.
- */
-#undef CONFIG_SYS_FLASH_EMPTY_INFO
-#endif
-
 /* I2C */
 
 #define I2C_PCA6408_BUS_NUM		1
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 0a8694f186e..2d48e14077d 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -354,18 +354,6 @@
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 
-#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
-/* Video */
-#define CONFIG_FSL_DIU_FB
-
-#ifdef CONFIG_FSL_DIU_FB
-#define CONFIG_FSL_DIU_CH7301
-#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
-#endif
-#endif
-
-/* I2C */
-
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR                0x70
 #define I2C_MUX_CH_DEFAULT      0x8
@@ -571,18 +559,11 @@
 #define FDTFILE		"t1042rdb/t1042d4rdb.dtb"
 #endif
 
-#ifdef CONFIG_FSL_DIU_FB
-#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
-#else
-#define DIU_ENVIRONMENT
-#endif
-
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"			\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 	"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
-	"video-mode=" __stringify(DIU_ENVIRONMENT) "\0"		\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
diff --git a/include/fsl_diu_fb.h b/include/fsl_diu_fb.h
deleted file mode 100644
index 139851ba1a8..00000000000
--- a/include/fsl_diu_fb.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007, 2011 Freescale Semiconductor, Inc.
- * Authors: York Sun <yorksun@freescale.com>
- *          Timur Tabi <timur@freescale.com>
- *
- * FSL DIU Framebuffer driver
- */
-
-int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix);
-
-/* Prototypes for external board-specific functions */
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port);
-void diu_set_pixel_clock(unsigned int pixclock);
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index f63eddfea4f..1edee279c4e 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -211,8 +211,6 @@ CONFIG_FSL_CADMUS
 CONFIG_FSL_CORENET
 CONFIG_FSL_CPLD
 CONFIG_FSL_DEVICE_DISABLE
-CONFIG_FSL_DIU_CH7301
-CONFIG_FSL_DIU_FB
 CONFIG_FSL_DSPI1
 CONFIG_FSL_ESDHC_PIN_MUX
 CONFIG_FSL_FIXED_MMC_LOCATION
@@ -1074,7 +1072,6 @@ CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
 CONFIG_SYS_DIRECT_FLASH_TFTP
 CONFIG_SYS_DISCOVER_PHY
-CONFIG_SYS_DIU_ADDR
 CONFIG_SYS_DPAA_DCE
 CONFIG_SYS_DPAA_FMAN
 CONFIG_SYS_DPAA_PME
