From patchwork Sat Jan 22 19:38:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Kettenis X-Patchwork-Id: 1583057 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=kpnmail.nl header.i=@kpnmail.nl header.a=rsa-sha256 header.s=kpnmail01 header.b=GSJ0DUMT; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Jh6626Scrz9sCD for ; Sun, 23 Jan 2022 06:40:10 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 954918390C; Sat, 22 Jan 2022 20:38:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=openbsd.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=kpnmail.nl header.i=@kpnmail.nl header.b="GSJ0DUMT"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id DB8FA835CA; Sat, 22 Jan 2022 20:38:43 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_SOFTFAIL autolearn=no autolearn_force=no version=3.4.2 Received: from ewsoutbound.kpnmail.nl (ewsoutbound.kpnmail.nl [195.121.94.183]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2AA9E83831 for ; Sat, 22 Jan 2022 20:38:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=openbsd.org Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=kettenis@openbsd.org X-KPN-MessageId: dfc4a559-7bba-11ec-a1d2-005056992ed3 Received: from smtp.kpnmail.nl (unknown [10.31.155.8]) by ewsoutbound.so.kpn.org (Halon) with ESMTPS id dfc4a559-7bba-11ec-a1d2-005056992ed3; Sat, 22 Jan 2022 20:38:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kpnmail.nl; s=kpnmail01; h=mime-version:message-id:date:subject:to:from; bh=wuqUIHe+zuZVhlw2nuXhDSJ/8gbQkpn/GhHKA6TFFT0=; b=GSJ0DUMT9vWFOgyp/rqnsioSudXQkXjpzlad9Rj++IrmoZYYHxzcT3OPxzNy+/ZYl1uEKAmbUwnUA Py1l+OGNEiDW/8PntHJvoLxr0xW6z1sVM0v85apn0B5hdSzPq8+kq27jIF7zwo3pk6FayOwy5htWOj Bgo4R9qEpOcXM85Y= X-KPN-VerifiedSender: No X-CMASSUN: 33|D1cUqq4Z9OkAn5h8E3Z0nLtxhOm3ZASF7hdFNxwpiW9jODKA2+hDMCXSdvTi0Mz Tmg7yOhzCUpt6h7Uj9m7g5g== X-Originating-IP: 83.163.83.176 Received: from copland.sibelius.xs4all.nl (sibelius.xs4all.nl [83.163.83.176]) by smtp.xs4all.nl (Halon) with ESMTPSA id f676085c-7bba-11ec-a897-00505699d6e5; Sat, 22 Jan 2022 20:39:07 +0100 (CET) From: Mark Kettenis To: u-boot@lists.denx.de Cc: sjg@chromium.org, jh80.chung@samsung.com, trini@konsulko.com, sven@svenpeter.dev, marcan@marcan.st, bmeng.cn@gmail.com, Mark Kettenis Subject: [PATCH v2 8/9] nvme: apple: Add driver for Apple NVMe storage controller Date: Sat, 22 Jan 2022 20:38:18 +0100 Message-Id: <20220122193819.84907-9-kettenis@openbsd.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220122193819.84907-1-kettenis@openbsd.org> References: <20220122193819.84907-1-kettenis@openbsd.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Add a driver for the NVMe storage controller integrated on Apple SoCs. This NVMe controller isn't PCI based and deviates from the NVMe standard in its implementation of the command submission queue and the integration of an NVMMU that needs to be managed. This commit tweaks the core NVMe code to support the linear command submission queue implemented by this controller. But setting up the submission queue and managing the NVMMU controller is handled by implementing the driver ops that were added in an earlier commit. Signed-off-by: Mark Kettenis Tested-on: firefly-rk3399 Tested-by: Mark Kettenis Tested on: Macbook Air M1 Tested-by: Simon Glass --- ChangeLog: v2: - Add comments - Change include paths to take advantage of SYS_SOC change configs/apple_m1_defconfig | 1 + drivers/nvme/Kconfig | 11 ++ drivers/nvme/Makefile | 1 + drivers/nvme/nvme_apple.c | 240 +++++++++++++++++++++++++++++++++++++ 4 files changed, 253 insertions(+) create mode 100644 drivers/nvme/nvme_apple.c diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index cb235e4e7d..1528217b17 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -11,6 +11,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_NET is not set # CONFIG_MMC is not set CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_NVME_APPLE=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_KEYBOARD=y diff --git a/drivers/nvme/Kconfig b/drivers/nvme/Kconfig index 78da444c8b..0cb465160b 100644 --- a/drivers/nvme/Kconfig +++ b/drivers/nvme/Kconfig @@ -10,6 +10,17 @@ config NVME This option enables support for NVM Express devices. It supports basic functions of NVMe (read/write). +config NVME_APPLE + bool "Apple NVMe controller support" + select NVME + help + This option enables support for the NVMe storage + controller integrated on Apple SoCs. This controller + isn't PCI-based based and deviates from the NVMe + standard implementation in its implementation of + the command submission queue and the integration + of an NVMMU that needs to be managed. + config NVME_PCI bool "NVM Express PCI device support" depends on PCI diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile index fad9724e17..fa7b619446 100644 --- a/drivers/nvme/Makefile +++ b/drivers/nvme/Makefile @@ -3,4 +3,5 @@ # Copyright (C) 2017, Bin Meng obj-y += nvme-uclass.o nvme.o nvme_show.o +obj-$(CONFIG_NVME_APPLE) += nvme_apple.o obj-$(CONFIG_NVME_PCI) += nvme_pci.o diff --git a/drivers/nvme/nvme_apple.c b/drivers/nvme/nvme_apple.c new file mode 100644 index 0000000000..6249fceb71 --- /dev/null +++ b/drivers/nvme/nvme_apple.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Mark Kettenis + */ + +#include +#include +#include +#include +#include "nvme.h" +#include + +#include +#include +#include + +/* ASC registers */ +#define REG_CPU_CTRL 0x0044 +#define REG_CPU_CTRL_RUN BIT(4) + +/* Apple NVMe registers */ +#define ANS_MAX_PEND_CMDS_CTRL 0x01210 +#define ANS_MAX_QUEUE_DEPTH 64 +#define ANS_BOOT_STATUS 0x01300 +#define ANS_BOOT_STATUS_OK 0xde71ce55 +#define ANS_MODESEL 0x01304 +#define ANS_UNKNOWN_CTRL 0x24008 +#define ANS_PRP_NULL_CHECK (1 << 11) +#define ANS_LINEAR_SQ_CTRL 0x24908 +#define ANS_LINEAR_SQ_CTRL_EN (1 << 0) +#define ANS_ASQ_DB 0x2490c +#define ANS_IOSQ_DB 0x24910 +#define ANS_NVMMU_NUM 0x28100 +#define ANS_NVMMU_BASE_ASQ 0x28108 +#define ANS_NVMMU_BASE_IOSQ 0x28110 +#define ANS_NVMMU_TCB_INVAL 0x28118 +#define ANS_NVMMU_TCB_STAT 0x28120 + +#define ANS_NVMMU_TCB_SIZE 0x4000 +#define ANS_NVMMU_TCB_PITCH 0x80 + +/* + * The Apple NVMe controller includes an IOMMU known as NVMMU. The + * NVMMU is programmed through an array of TCBs. These TCBs are paired + * with the corresponding slot in the submission queues and need to be + * configured with the command details before a command is allowed to + * execute. This is necessary even for commands that don't do DMA. + */ +struct ans_nvmmu_tcb { + u8 opcode; + u8 flags; + u8 slot; + u8 pad0; + u32 prpl_len; + u8 pad1[16]; + u64 prp1; + u64 prp2; +}; + +#define ANS_NVMMU_TCB_WRITE BIT(0) +#define ANS_NVMMU_TCB_READ BIT(1) + +struct apple_nvme_priv { + struct nvme_dev ndev; + void *base; /* NVMe registers */ + void *asc; /* ASC registers */ + struct reset_ctl_bulk resets; /* ASC reset */ + struct mbox_chan chan; + struct ans_nvmmu_tcb *tcbs[NVME_Q_NUM]; /* Submission queue TCBs */ + u32 __iomem *q_db[NVME_Q_NUM]; /* Submission queue doorbell */ +}; + +static int apple_nvme_setup_queue(struct nvme_queue *nvmeq) +{ + struct apple_nvme_priv *priv = + container_of(nvmeq->dev, struct apple_nvme_priv, ndev); + struct nvme_dev *dev = nvmeq->dev; + + switch (nvmeq->qid) { + case NVME_ADMIN_Q: + case NVME_IO_Q: + break; + default: + return -EINVAL; + } + + priv->tcbs[nvmeq->qid] = (void *)memalign(4096, ANS_NVMMU_TCB_SIZE); + memset((void *)priv->tcbs[nvmeq->qid], 0, ANS_NVMMU_TCB_SIZE); + + switch (nvmeq->qid) { + case NVME_ADMIN_Q: + priv->q_db[nvmeq->qid] = + ((void __iomem *)dev->bar) + ANS_ASQ_DB; + nvme_writeq((ulong)priv->tcbs[nvmeq->qid], + ((void __iomem *)dev->bar) + ANS_NVMMU_BASE_ASQ); + break; + case NVME_IO_Q: + priv->q_db[nvmeq->qid] = + ((void __iomem *)dev->bar) + ANS_IOSQ_DB; + nvme_writeq((ulong)priv->tcbs[nvmeq->qid], + ((void __iomem *)dev->bar) + ANS_NVMMU_BASE_IOSQ); + break; + } + + return 0; +} + +static void apple_nvme_submit_cmd(struct nvme_queue *nvmeq, + struct nvme_command *cmd) +{ + struct apple_nvme_priv *priv = + container_of(nvmeq->dev, struct apple_nvme_priv, ndev); + struct ans_nvmmu_tcb *tcb; + u16 tail = nvmeq->sq_tail; + + tcb = ((void *)priv->tcbs[nvmeq->qid]) + tail * ANS_NVMMU_TCB_PITCH; + memset(tcb, 0, sizeof(*tcb)); + tcb->opcode = cmd->common.opcode; + tcb->flags = ANS_NVMMU_TCB_WRITE | ANS_NVMMU_TCB_READ; + tcb->slot = tail; + tcb->prpl_len = cmd->rw.length; + tcb->prp1 = cmd->common.prp1; + tcb->prp2 = cmd->common.prp2; + + writel(tail, priv->q_db[nvmeq->qid]); +} + +static void apple_nvme_complete_cmd(struct nvme_queue *nvmeq, + struct nvme_command *cmd) +{ + struct apple_nvme_priv *priv = + container_of(nvmeq->dev, struct apple_nvme_priv, ndev); + struct ans_nvmmu_tcb *tcb; + u16 tail = nvmeq->sq_tail; + + tcb = ((void *)priv->tcbs[nvmeq->qid]) + tail * ANS_NVMMU_TCB_PITCH; + memset(tcb, 0, sizeof(*tcb)); + writel(tail, ((void __iomem *)nvmeq->dev->bar) + ANS_NVMMU_TCB_INVAL); + readl(((void __iomem *)nvmeq->dev->bar) + ANS_NVMMU_TCB_STAT); + + if (++tail == nvmeq->q_depth) + tail = 0; + nvmeq->sq_tail = tail; +} + +static int apple_nvme_probe(struct udevice *dev) +{ + struct apple_nvme_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + u32 ctrl, stat; + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + addr = dev_read_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + priv->asc = map_sysmem(addr, 0); + + ret = reset_get_bulk(dev, &priv->resets); + if (ret < 0) + return ret; + + ret = mbox_get_by_index(dev, 0, &priv->chan); + if (ret < 0) + return ret; + + ctrl = readl(priv->asc + REG_CPU_CTRL); + writel(ctrl | REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL); + + ret = apple_rtkit_init(&priv->chan); + if (ret < 0) + return ret; + + ret = readl_poll_sleep_timeout(priv->base + ANS_BOOT_STATUS, stat, + (stat == ANS_BOOT_STATUS_OK), 100, + 500000); + if (ret < 0) { + printf("%s: NVMe firmware didn't boot\n", __func__); + return -ETIMEDOUT; + } + + writel(ANS_LINEAR_SQ_CTRL_EN, priv->base + ANS_LINEAR_SQ_CTRL); + writel(((ANS_MAX_QUEUE_DEPTH << 16) | ANS_MAX_QUEUE_DEPTH), + priv->base + ANS_MAX_PEND_CMDS_CTRL); + + writel(readl(priv->base + ANS_UNKNOWN_CTRL) & ~ANS_PRP_NULL_CHECK, + priv->base + ANS_UNKNOWN_CTRL); + + strcpy(priv->ndev.vendor, "Apple"); + + writel((ANS_NVMMU_TCB_SIZE / ANS_NVMMU_TCB_PITCH) - 1, + priv->base + ANS_NVMMU_NUM); + writel(0, priv->base + ANS_MODESEL); + + priv->ndev.bar = priv->base; + return nvme_init(dev); +} + +static int apple_nvme_remove(struct udevice *dev) +{ + struct apple_nvme_priv *priv = dev_get_priv(dev); + u32 ctrl; + + nvme_shutdown(dev); + + apple_rtkit_shutdown(&priv->chan, APPLE_RTKIT_PWR_STATE_SLEEP); + + ctrl = readl(priv->asc + REG_CPU_CTRL); + writel(ctrl & ~REG_CPU_CTRL_RUN, priv->asc + REG_CPU_CTRL); + + reset_assert_bulk(&priv->resets); + reset_deassert_bulk(&priv->resets); + + return 0; +} + +static const struct nvme_ops apple_nvme_ops = { + .setup_queue = apple_nvme_setup_queue, + .submit_cmd = apple_nvme_submit_cmd, + .complete_cmd = apple_nvme_complete_cmd, +}; + +static const struct udevice_id apple_nvme_ids[] = { + { .compatible = "apple,nvme-ans2" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(apple_nvme) = { + .name = "apple_nvme", + .id = UCLASS_NVME, + .of_match = apple_nvme_ids, + .priv_auto = sizeof(struct apple_nvme_priv), + .probe = apple_nvme_probe, + .remove = apple_nvme_remove, + .ops = &apple_nvme_ops, + .flags = DM_FLAG_OS_PREPARE, +};