diff mbox series

[02/13] arm: dts: add the Purism devicetree files

Message ID 20220117150735.218886-3-angus@akkea.ca
State Changes Requested
Delegated to: Stefano Babic
Headers show
Series Add support for the Purism Librem5 Phone | expand

Commit Message

Angus Ainslie Jan. 17, 2022, 3:07 p.m. UTC 
Initial commit of Librem5 devicetree files

Signed-off-by: Angus Ainslie <angus@akkea.ca>
---
 arch/arm/dts/Makefile                   |   3 +-
 arch/arm/dts/imx8mq-librem5-u-boot.dtsi | 134 ++++++
 arch/arm/dts/imx8mq-librem5.dts         | 593 ++++++++++++++++++++++++
 3 files changed, 729 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx8mq-librem5-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mq-librem5.dts

Comments

Tom Rini Jan. 17, 2022, 4:59 p.m. UTC | #1 
On Mon, Jan 17, 2022 at 07:07:24AM -0800, Angus Ainslie wrote:

> Initial commit of Librem5 devicetree files
> 
> Signed-off-by: Angus Ainslie <angus@akkea.ca>

Please note what kernel release the not -u-boot.dtsi files are a copy
from, as they need to be copies and not modified, thanks.
Angus Ainslie Jan. 17, 2022, 5:51 p.m. UTC | #2 
Hi Tom,

On 2022-01-17 08:59, Tom Rini wrote:
> On Mon, Jan 17, 2022 at 07:07:24AM -0800, Angus Ainslie wrote:
> 
>> Initial commit of Librem5 devicetree files
>> 
>> Signed-off-by: Angus Ainslie <angus@akkea.ca>
> 
> Please note what kernel release the not -u-boot.dtsi files are a copy
> from, as they need to be copies and not modified, thanks.

There's an issue with adding the devicetree from the 5.16 kernel.

I get a compilation error due to a :missing .h in the devicetree files:

In file included from arch/arm/dts/imx8mq-librem5-r3.dtsi:11,
                  from arch/arm/dts/.imx8mq-librem5.dtb.pre.tmp:6:
arch/arm/dts/imx8mq-librem5.dtsi:13:10: fatal error: 
dt-bindings/rfkill/rfkill.h: No such file or directory
    13 | #include "dt-bindings/rfkill/rfkill.h"
       |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Should that get added to the u-boot source as well or should I modify 
the dts to remove this ?

For the kernel we also have 4 different dts files for the differences in 
PCB versions. For u-boot we don't need the differentiation as it deals 
with things like camera rotation and prox sensor sensitivity.

There's 2 ways to solve the this I think.

1) just use the latest librem5 dts file which is made up of 3 different 
dts(i) files.
2) have a defconfig for each of the different PCB versions.

Do you have a preference ?

Thanks
Angus
Tom Rini Jan. 17, 2022, 6:25 p.m. UTC | #3 
On Mon, Jan 17, 2022 at 09:51:24AM -0800, Angus Ainslie wrote:
> Hi Tom,
> 
> On 2022-01-17 08:59, Tom Rini wrote:
> > On Mon, Jan 17, 2022 at 07:07:24AM -0800, Angus Ainslie wrote:
> > 
> > > Initial commit of Librem5 devicetree files
> > > 
> > > Signed-off-by: Angus Ainslie <angus@akkea.ca>
> > 
> > Please note what kernel release the not -u-boot.dtsi files are a copy
> > from, as they need to be copies and not modified, thanks.
> 
> There's an issue with adding the devicetree from the 5.16 kernel.
> 
> I get a compilation error due to a :missing .h in the devicetree files:
> 
> In file included from arch/arm/dts/imx8mq-librem5-r3.dtsi:11,
>                  from arch/arm/dts/.imx8mq-librem5.dtb.pre.tmp:6:
> arch/arm/dts/imx8mq-librem5.dtsi:13:10: fatal error:
> dt-bindings/rfkill/rfkill.h: No such file or directory
>    13 | #include "dt-bindings/rfkill/rfkill.h"
>       |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 
> Should that get added to the u-boot source as well or should I modify the
> dts to remove this ?

Import the missing binding(s) in a separate commit first please.

> For the kernel we also have 4 different dts files for the differences in PCB
> versions. For u-boot we don't need the differentiation as it deals with
> things like camera rotation and prox sensor sensitivity.
> 
> There's 2 ways to solve the this I think.
> 
> 1) just use the latest librem5 dts file which is made up of 3 different
> dts(i) files.
> 2) have a defconfig for each of the different PCB versions.
> 
> Do you have a preference ?

Can you tell the revision at run-time?  We have examples of boards that
can and will include revA.dtb and revB.dtb and select the correct one at
run time (and start with something that works on revA and revB).
Angus Ainslie Jan. 17, 2022, 6:52 p.m. UTC | #4 
On 2022-01-17 10:25, Tom Rini wrote:
> On Mon, Jan 17, 2022 at 09:51:24AM -0800, Angus Ainslie wrote:
>> 
>> There's 2 ways to solve the this I think.
>> 
>> 1) just use the latest librem5 dts file which is made up of 3 
>> different
>> dts(i) files.
>> 2) have a defconfig for each of the different PCB versions.
>> 
>> Do you have a preference ?
> 
> Can you tell the revision at run-time?  We have examples of boards that
> can and will include revA.dtb and revB.dtb and select the correct one 
> at
> run time (and start with something that works on revA and revB).

Due to some changes by NXP in the fuse section of the imx8mq we can't 
reliably detect some of the earlier revisions.

Going forward we should be able to using this

https://lists.denx.de/pipermail/u-boot/2021-November/468419.html

But that will be post r4 boards.
Tom Rini Jan. 17, 2022, 7:42 p.m. UTC | #5 
On Mon, Jan 17, 2022 at 10:52:42AM -0800, Angus Ainslie wrote:
> On 2022-01-17 10:25, Tom Rini wrote:
> > On Mon, Jan 17, 2022 at 09:51:24AM -0800, Angus Ainslie wrote:
> > > 
> > > There's 2 ways to solve the this I think.
> > > 
> > > 1) just use the latest librem5 dts file which is made up of 3
> > > different
> > > dts(i) files.
> > > 2) have a defconfig for each of the different PCB versions.
> > > 
> > > Do you have a preference ?
> > 
> > Can you tell the revision at run-time?  We have examples of boards that
> > can and will include revA.dtb and revB.dtb and select the correct one at
> > run time (and start with something that works on revA and revB).
> 
> Due to some changes by NXP in the fuse section of the imx8mq we can't
> reliably detect some of the earlier revisions.
> 
> Going forward we should be able to using this
> 
> https://lists.denx.de/pipermail/u-boot/2021-November/468419.html
> 
> But that will be post r4 boards.

Ah "fun".  I guess I'd lean towards #1 then if you think that'll be easy
enough on the end users too.
diff mbox series

Patch

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aeaec7136f..7a829522c8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -912,7 +912,8 @@  dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mq-phanbell.dtb \
 	imx8mp-evk.dtb \
 	imx8mp-phyboard-pollux-rdk.dtb \
-	imx8mq-pico-pi.dtb
+	imx8mq-pico-pi.dtb \
+	imx8mq-librem5.dtb
 
 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
 	imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx8mq-librem5-u-boot.dtsi b/arch/arm/dts/imx8mq-librem5-u-boot.dtsi
new file mode 100644
index 0000000000..e3f780ca75
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5-u-boot.dtsi
@@ -0,0 +1,134 @@ 
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+	binman: binman {
+		multiple-images;
+	};
+};
+
+&binman {
+	u-boot-spl-ddr {
+		filename = "u-boot-spl-ddr.bin";
+		pad-byte = <0xff>;
+		align-size = <4>;
+		align = <4>;
+
+		u-boot-spl {
+			align-end = <4>;
+		};
+
+		blob_1: blob-ext@1 {
+			filename = "lpddr4_pmu_train_1d_imem.bin";
+			size = <0x8000>;
+		};
+
+		blob_2: blob-ext@2 {
+			filename = "lpddr4_pmu_train_1d_dmem.bin";
+			size = <0x4000>;
+		};
+
+		blob_3: blob-ext@3 {
+			filename = "lpddr4_pmu_train_2d_imem.bin";
+			size = <0x8000>;
+		};
+
+		blob_4: blob-ext@4 {
+			filename = "lpddr4_pmu_train_2d_dmem.bin";
+			size = <0x4000>;
+		};
+	};
+
+	spl {
+		filename = "spl.bin";
+
+		mkimage {
+			args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+			blob {
+				filename = "u-boot-spl-ddr.bin";
+			};
+		};
+	};
+
+	itb {
+		filename = "u-boot.itb";
+
+		fit {
+			description = "Configuration to load ATF before U-Boot";
+			#address-cells = <1>;
+			fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+			images {
+				uboot {
+					description = "U-Boot (64-bit)";
+					type = "standalone";
+					arch = "arm64";
+					compression = "none";
+					load = <CONFIG_SYS_TEXT_BASE>;
+
+					uboot_blob: blob-ext {
+						filename = "u-boot-nodtb.bin";
+					};
+				};
+
+				atf {
+					description = "ARM Trusted Firmware";
+					type = "firmware";
+					arch = "arm64";
+					compression = "none";
+					load = <0x910000>;
+					entry = <0x910000>;
+
+					atf_blob: blob-ext {
+						filename = "bl31.bin";
+					};
+				};
+
+				fdt {
+					description = "NAME";
+					type = "flat_dt";
+					compression = "none";
+
+					uboot_fdt_blob: blob-ext {
+						filename = "u-boot.dtb";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf";
+
+				conf {
+					description = "NAME";
+					firmware = "uboot";
+					loadables = "atf";
+					fdt = "fdt";
+				};
+			};
+		};
+	};
+
+	imx-boot {
+		filename = "flash.bin";
+		pad-byte = <0x00>;
+
+		spl: blob-ext@1 {
+			offset = <0x0>;
+			filename = "spl.bin";
+		};
+
+		uboot: blob-ext@2 {
+			offset = <0x57c00>;
+			filename = "u-boot.itb";
+		};
+	};
+};
+
+&usdhc1 {
+	mmc-hs400-1_8v;
+};
+
+&usdhc2 {
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+};
diff --git a/arch/arm/dts/imx8mq-librem5.dts b/arch/arm/dts/imx8mq-librem5.dts
new file mode 100644
index 0000000000..93939df18f
--- /dev/null
+++ b/arch/arm/dts/imx8mq-librem5.dts
@@ -0,0 +1,593 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * Copyright (C) 2021 Purism SPC
+ *
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+
+/ {
+	model = "Librem 5";
+	compatible = "purism,librem5", "fsl,imx8mq";
+
+	chosen {
+		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
+		stdout-path = &uart1;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			u-boot,dm-spl;
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pinctrl_led>;
+
+		ledr {
+			label = "LED_R";
+			gpios = <&gpio5 3 0>;
+		};
+		ledg {
+			label = "LED_G";
+			gpios = <&gpio5 2 0>;
+		};
+		ledb {
+			label = "LED_B";
+			gpios = <&gpio1 13 0>;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_hog1: hoggrp1 {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x83 /*	CAMERA_PWR_EN_3V3 */
+			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x83 /*	TF_PWR_3V3_EN */
+			MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4	0x83 /*	AUDIO_POWER_EN_3V3 */
+			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x83 /*	DSI_EN_3V3 */
+			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x3f
+			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x3f
+			MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x83 /* HUB_PWR_3V3_EN */
+			MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16	0xC0
+			MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17	0xC0
+			MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20	0x83 /*	DSI_BIAS_EN */
+			MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23	0x83 /*	FLASH_EN */
+		>;
+	};
+
+	pinctrl_hog3: hoggrp3 {
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x3 /* CHG_EN */
+			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x3 /* CHG_OTG_OUT_EN */
+			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x83 /* WIFI3V3_EN */
+			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x83 /* GPS3V3_EN */
+			MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14		0x83 /* BACKLINGE_EN */
+			MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18		0x83 /* 4G_PWR_EN */
+			MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24		0x83 /* TPS_RESET */
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000003f
+			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000003f
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000001f
+			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000001f
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000001f
+			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000001f
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x4000003f
+			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x4000003f
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x82
+			MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x19
+			MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x82
+			MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x80
+		>;
+	};
+
+	pinctrl_led: ledgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3		0x16 /* LED_R */
+			MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x16 /* LED_G */
+			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16 /* LED_B */
+		>;
+	};
+
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			 MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x80 /* PMIC_NINT */
+		>;
+	};
+
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5     0x83 /* MOTO */
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79
+			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+	       fsl,pins = <
+		       MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
+		       MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
+	       >;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x79
+			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x79
+			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x19
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+	       fsl,pins = <
+		       MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49
+		       MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49
+		       MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B		0x49
+		       MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x49
+	       >;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8f
+			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcf
+			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcf
+			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcf
+			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcf
+			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcf
+			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcf
+			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcf
+			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcf
+			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcf
+			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8f
+			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41    /* WIFI_nRST */
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8f
+			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcf
+			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcf
+			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcf
+			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcf
+			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcf
+			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+		>;
+	};
+
+	pinctrl_sai2: sai2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
+			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
+			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
+			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
+			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xd6
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+		>;
+	};
+};
+
+&gpio1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog1>;
+
+	csi_en {
+		gpio-hog;
+		output-low;
+		gpios = <0 GPIO_ACTIVE_HIGH>;
+		line-name = "csi_en";
+	};
+	sdcard_pwr {
+		gpio-hog;
+		output-high;
+		gpios = <3 GPIO_ACTIVE_HIGH>;
+	};
+	audio_pwr {
+		gpio-hog;
+		output-high;
+		gpios = <4 GPIO_ACTIVE_HIGH>;
+	};
+	hub_nreset {
+		gpio-hog;
+		output-high;
+		gpios = <12 GPIO_ACTIVE_HIGH>;
+		line-name = "hub_nreset";
+	};
+	hub_pwr {
+		gpio-hog;
+		output-high;
+		gpios = <14 GPIO_ACTIVE_HIGH>;
+		line-name = "hub_pwr";
+	};
+};
+
+&gpio3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog3>;
+	status = "okay";
+
+	chg_en {
+		gpio-hog;
+		output-low;
+		gpios = <17 GPIO_ACTIVE_HIGH>;
+	};
+	tps_reset {
+		gpio-hog;
+		output-low;
+		gpios = <24 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	pmic@4b {
+		compatible = "rohm,bd71837";
+		reg = <0x4b>;
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <7 GPIO_ACTIVE_LOW>;
+		rohm,reset-snvs-powered;
+		u-boot,dm-pre-reloc;
+		regulators {
+			buck1_reg: BUCK1 {
+				regulator-name = "buck1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-ramp-delay = <1250>;
+				rohm,dvs-run-voltage = <900000>;
+				rohm,dvs-idle-voltage = <850000>;
+				rohm,dvs-suspend-voltage = <800000>;
+				regulator-always-on;
+			};
+
+			buck2_reg: BUCK2 {
+				regulator-name = "buck2";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-ramp-delay = <1250>;
+				rohm,dvs-run-voltage = <1000000>;
+				rohm,dvs-idle-voltage = <900000>;
+				regulator-always-on;
+			};
+
+			buck3_reg: BUCK3 {
+				regulator-name = "buck3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				rohm,dvs-run-voltage = <900000>;
+				regulator-always-on;
+			};
+
+			buck4_reg: BUCK4 {
+				regulator-name = "buck4";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				rohm,dvs-run-voltage = <1000000>;
+			};
+
+			buck5_reg: BUCK5 {
+				regulator-name = "buck5";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: BUCK6 {
+				regulator-name = "buck6";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck7_reg: BUCK7 {
+				regulator-name = "buck7";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck8_reg: BUCK8 {
+				regulator-name = "buck8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: LDO1 {
+				regulator-name = "ldo1";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				/* leave on for snvs power button */
+				regulator-always-on;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-name = "ldo2";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				/* leave on for snvs power button */
+				regulator-always-on;
+			};
+
+			ldo3_reg: LDO3 {
+				regulator-name = "ldo3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: LDO4 {
+				regulator-name = "ldo4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5_reg: LDO5 {
+				/* VDD_PHY_0V9 - MIPI and HDMI domains */
+				regulator-name = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			ldo6_reg: LDO6 {
+				/* VDD_PHY_0V9 - MIPI, HDMI and USB domains */
+				regulator-name = "ldo6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo7_reg: LDO7 {
+				/* VDD_PHY_3V3 - USB domain */
+				regulator-name = "ldo7";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "okay";
+};
+
+&ecspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	flash0: winbond@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <29000000>;
+	};
+};
+
+&uart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART1_ROOT>;
+	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+	status = "okay";
+};
+
+&uart3 { /* BT */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART3_ROOT>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+	fsl,uart-has-rtscts;
+	status = "disabled";
+};
+
+&usdhc1 {
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	broken-cd;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	compatible = "snps,dwc3-gadget";
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+	status = "okay";
+	dr_mode = "peripheral";
+	snps,dis_u2_susphy_quirk;
+	snps,dis_u3_susphy_quirk;
+	maximum-speed = "high-speed";
+};
+
+&usb3_phy1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+	dr_mode = "host";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};