diff mbox series

[v7,01/15] crypto/fsl: Add support for CAAM Job ring driver model

Message ID 20211207074129.10955-2-gaurav.jain@nxp.com
State Changes Requested
Delegated to: Stefano Babic
Headers show
Series Add CAAM driver model support | expand

Commit Message

Gaurav Jain Dec. 7, 2021, 7:41 a.m. UTC 
added device tree support for job ring driver.
sec is initialized based on job ring information processed
from device tree.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
 drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++++--------------
 drivers/crypto/fsl/jr.h |  19 +++
 2 files changed, 231 insertions(+), 111 deletions(-)

Comments

Simon Glass Dec. 28, 2021, 8:32 a.m. UTC | #1 
Hi Gaurav,

On Tue, 7 Dec 2021 at 00:42, Gaurav Jain <gaurav.jain@nxp.com> wrote:
>
> added device tree support for job ring driver.
> sec is initialized based on job ring information processed
> from device tree.
>
> Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
> ---
>  drivers/crypto/fsl/jr.c | 323 ++++++++++++++++++++++++++--------------
>  drivers/crypto/fsl/jr.h |  19 +++
>  2 files changed, 231 insertions(+), 111 deletions(-)
>
> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
> index 22b649219e..441550f348 100644
> --- a/drivers/crypto/fsl/jr.c
> +++ b/drivers/crypto/fsl/jr.c
> @@ -1,7 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
>   * Copyright 2008-2014 Freescale Semiconductor, Inc.
> - * Copyright 2018 NXP
> + * Copyright 2018, 2021 NXP
>   *
>   * Based on CAAM driver in drivers/crypto/caam in Linux
>   */
> @@ -11,7 +11,6 @@
>  #include <linux/kernel.h>
>  #include <log.h>
>  #include <malloc.h>
> -#include "fsl_sec.h"
>  #include "jr.h"
>  #include "jobdesc.h"
>  #include "desc_constr.h"
> @@ -21,8 +20,11 @@
>  #include <asm/cache.h>
>  #include <asm/fsl_pamu.h>
>  #endif
> +#include <dm.h>
>  #include <dm/lists.h>
>  #include <linux/delay.h>
> +#include <dm/root.h>
> +#include <dm/device-internal.h>

These should go up one line.

https://www.denx.de/wiki/U-Boot/CodingStyle

Re the uclass, this is using MISC. What operations are actually
supported? I am still not sure why this doesn't deserve its own
uclass.


[..]

> diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
> index 1047aa772c..c5e5ed5c26 100644
> --- a/drivers/crypto/fsl/jr.h
> +++ b/drivers/crypto/fsl/jr.h
> @@ -1,6 +1,7 @@
>  /* SPDX-License-Identifier: GPL-2.0+ */
>  /*
>   * Copyright 2008-2014 Freescale Semiconductor, Inc.
> + * Copyright 2021 NXP
>   *
>   */
>
> @@ -8,7 +9,9 @@
>  #define __JR_H
>
>  #include <linux/compiler.h>
> +#include "fsl_sec.h"
>  #include "type.h"
> +#include <misc.h>
>
>  #define JR_SIZE 4
>  /* Timeout currently defined as 10 sec */
> @@ -35,12 +38,21 @@
>  #define JRSLIODN_SHIFT         0
>  #define JRSLIODN_MASK          0x00000fff
>
> +#define JRDID_MS_PRIM_DID      BIT(0)
> +#define JRDID_MS_PRIM_TZ       BIT(4)
> +#define JRDID_MS_TZ_OWN                BIT(15)
> +
>  #define JQ_DEQ_ERR             -1
>  #define JQ_DEQ_TO_ERR          -2
>  #define JQ_ENQ_ERR             -3

Good idea to put brackets around #defines that are a -ve number.

>
>  #define RNG4_MAX_HANDLES       2
>
> +enum {
> +       /* Run caam jobring descriptor(in buf) */
> +       CAAM_JR_RUN_DESC,
> +};
> +
>  struct op_ring {
>         caam_dma_addr_t desc;
>         uint32_t status;
> @@ -102,6 +114,13 @@ struct result {
>         uint32_t status;
>  };
>
> +struct caam_regs {
> +       ccsr_sec_t *sec;
> +       struct jr_regs *regs;
> +       u8 jrid;
> +       struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> +};

Don't forget to comment the structs.
> +
>  void caam_jr_strstatus(u32 status);
>  int run_descriptor_jr(uint32_t *desc);

and exported functions (normally drivers shouldn't have these).

>
> --
> 2.17.1
>

Regards,
Simon

Regards,
Simon
Gaurav Jain Jan. 7, 2022, 5:53 a.m. UTC | #2 
Hi

> -----Original Message-----
> From: Simon Glass <sjg@chromium.org>
> Sent: Tuesday, December 28, 2021 2:02 PM
> To: Gaurav Jain <gaurav.jain@nxp.com>
> Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Stefano Babic
> <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan
> <peng.fan@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> Subject: [EXT] Re: [PATCH v7 01/15] crypto/fsl: Add support for CAAM Job ring
> driver model
> 
> Caution: EXT Email
> 
> Hi Gaurav,
> 
> On Tue, 7 Dec 2021 at 00:42, Gaurav Jain <gaurav.jain@nxp.com> wrote:
> >
> > added device tree support for job ring driver.
> > sec is initialized based on job ring information processed from device
> > tree.
> >
> > Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> > Reviewed-by: Ye Li <ye.li@nxp.com>
> > ---
> >  drivers/crypto/fsl/jr.c | 323
> > ++++++++++++++++++++++++++--------------
> >  drivers/crypto/fsl/jr.h |  19 +++
> >  2 files changed, 231 insertions(+), 111 deletions(-)
> >
> > diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index
> > 22b649219e..441550f348 100644
> > --- a/drivers/crypto/fsl/jr.c
> > +++ b/drivers/crypto/fsl/jr.c
> > @@ -1,7 +1,7 @@
> >  // SPDX-License-Identifier: GPL-2.0+
> >  /*
> >   * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > - * Copyright 2018 NXP
> > + * Copyright 2018, 2021 NXP
> >   *
> >   * Based on CAAM driver in drivers/crypto/caam in Linux
> >   */
> > @@ -11,7 +11,6 @@
> >  #include <linux/kernel.h>
> >  #include <log.h>
> >  #include <malloc.h>
> > -#include "fsl_sec.h"
> >  #include "jr.h"
> >  #include "jobdesc.h"
> >  #include "desc_constr.h"
> > @@ -21,8 +20,11 @@
> >  #include <asm/cache.h>
> >  #include <asm/fsl_pamu.h>
> >  #endif
> > +#include <dm.h>
> >  #include <dm/lists.h>
> >  #include <linux/delay.h>
> > +#include <dm/root.h>
> > +#include <dm/device-internal.h>
> 
> These should go up one line.
> 
Ok. Will do in next version.

> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.de
> nx.de%2Fwiki%2FU-
> Boot%2FCodingStyle&amp;data=04%7C01%7Cgaurav.jain%40nxp.com%7C021c
> 004f07e44d796a7408d9c9dc9e41%7C686ea1d3bc2b4c6fa92cd99c5c301635%7
> C0%7C0%7C637762771646492648%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC
> 4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&a
> mp;sdata=HOzWAz8vqKuavYOZopqZf3iLD5dbenfY2UEF%2BO0h1W4%3D&amp;r
> eserved=0
> 
> Re the uclass, this is using MISC. What operations are actually supported? I am
> still not sure why this doesn't deserve its own uclass.
> 
Ioctl operation(caam_jr_ioctl) provided by MISC Uclass is sufficient for this driver.
I do not see a need for introducing a new Uclass to support this driver.

> 
> [..]
> 
> > diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index
> > 1047aa772c..c5e5ed5c26 100644
> > --- a/drivers/crypto/fsl/jr.h
> > +++ b/drivers/crypto/fsl/jr.h
> > @@ -1,6 +1,7 @@
> >  /* SPDX-License-Identifier: GPL-2.0+ */
> >  /*
> >   * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > + * Copyright 2021 NXP
> >   *
> >   */
> >
> > @@ -8,7 +9,9 @@
> >  #define __JR_H
> >
> >  #include <linux/compiler.h>
> > +#include "fsl_sec.h"
> >  #include "type.h"
> > +#include <misc.h>
> >
> >  #define JR_SIZE 4
> >  /* Timeout currently defined as 10 sec */ @@ -35,12 +38,21 @@
> >  #define JRSLIODN_SHIFT         0
> >  #define JRSLIODN_MASK          0x00000fff
> >
> > +#define JRDID_MS_PRIM_DID      BIT(0)
> > +#define JRDID_MS_PRIM_TZ       BIT(4)
> > +#define JRDID_MS_TZ_OWN                BIT(15)
> > +
> >  #define JQ_DEQ_ERR             -1
> >  #define JQ_DEQ_TO_ERR          -2
> >  #define JQ_ENQ_ERR             -3
> 
> Good idea to put brackets around #defines that are a -ve number.
Will do in next version.
> 
> >
> >  #define RNG4_MAX_HANDLES       2
> >
> > +enum {
> > +       /* Run caam jobring descriptor(in buf) */
> > +       CAAM_JR_RUN_DESC,
> > +};
> > +
> >  struct op_ring {
> >         caam_dma_addr_t desc;
> >         uint32_t status;
> > @@ -102,6 +114,13 @@ struct result {
> >         uint32_t status;
> >  };
> >
> > +struct caam_regs {
> > +       ccsr_sec_t *sec;
> > +       struct jr_regs *regs;
> > +       u8 jrid;
> > +       struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> > +};
> 
> Don't forget to comment the structs.
Will add in next version.

> > +
> >  void caam_jr_strstatus(u32 status);
> >  int run_descriptor_jr(uint32_t *desc);
> 
> and exported functions (normally drivers shouldn't have these).
Yes I agree. Since run_descriptor_jr() is already in use.
I am planning a separate patch to move other user of run_descriptor_jr() to caam_jr_ioctl().

Regards
Gaurav Jain
> 
> >
> > --
> > 2.17.1
> >
> 
> Regards,
> Simon
> 
> Regards,
> Simon
Simon Glass Jan. 8, 2022, 2:53 p.m. UTC | #3 
Hi Gaurav,

On Thu, 6 Jan 2022 at 22:54, Gaurav Jain <gaurav.jain@nxp.com> wrote:
>
> Hi
>
> > -----Original Message-----
> > From: Simon Glass <sjg@chromium.org>
> > Sent: Tuesday, December 28, 2021 2:02 PM
> > To: Gaurav Jain <gaurav.jain@nxp.com>
> > Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Stefano Babic
> > <sbabic@denx.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan
> > <peng.fan@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Ye Li
> > <ye.li@nxp.com>; Horia Geanta <horia.geanta@nxp.com>; Ji Luo
> > <ji.luo@nxp.com>; Franck Lenormand <franck.lenormand@nxp.com>; Silvano Di
> > Ninno <silvano.dininno@nxp.com>; Sahil Malhotra <sahil.malhotra@nxp.com>;
> > Pankaj Gupta <pankaj.gupta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; dl-
> > uboot-imx <uboot-imx@nxp.com>; Shengzhou Liu <shengzhou.liu@nxp.com>;
> > Mingkai Hu <mingkai.hu@nxp.com>; Rajesh Bhagat <rajesh.bhagat@nxp.com>;
> > Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Wasim Khan
> > <wasim.khan@nxp.com>; Alison Wang <alison.wang@nxp.com>; Pramod
> > Kumar <pramod.kumar_1@nxp.com>; Andy Tang <andy.tang@nxp.com>;
> > Adrian Alonso <adrian.alonso@nxp.com>; Vladimir Oltean <olteanv@gmail.com>
> > Subject: [EXT] Re: [PATCH v7 01/15] crypto/fsl: Add support for CAAM Job ring
> > driver model
> >
> > Caution: EXT Email
> >
> > Hi Gaurav,
> >
> > On Tue, 7 Dec 2021 at 00:42, Gaurav Jain <gaurav.jain@nxp.com> wrote:
> > >
> > > added device tree support for job ring driver.
> > > sec is initialized based on job ring information processed from device
> > > tree.
> > >
> > > Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
> > > Reviewed-by: Ye Li <ye.li@nxp.com>
> > > ---
> > >  drivers/crypto/fsl/jr.c | 323
> > > ++++++++++++++++++++++++++--------------
> > >  drivers/crypto/fsl/jr.h |  19 +++
> > >  2 files changed, 231 insertions(+), 111 deletions(-)
> > >
> > > diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index
> > > 22b649219e..441550f348 100644
> > > --- a/drivers/crypto/fsl/jr.c
> > > +++ b/drivers/crypto/fsl/jr.c
> > > @@ -1,7 +1,7 @@
> > >  // SPDX-License-Identifier: GPL-2.0+
> > >  /*
> > >   * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > > - * Copyright 2018 NXP
> > > + * Copyright 2018, 2021 NXP
> > >   *
> > >   * Based on CAAM driver in drivers/crypto/caam in Linux
> > >   */
> > > @@ -11,7 +11,6 @@
> > >  #include <linux/kernel.h>
> > >  #include <log.h>
> > >  #include <malloc.h>
> > > -#include "fsl_sec.h"
> > >  #include "jr.h"
> > >  #include "jobdesc.h"
> > >  #include "desc_constr.h"
> > > @@ -21,8 +20,11 @@
> > >  #include <asm/cache.h>
> > >  #include <asm/fsl_pamu.h>
> > >  #endif
> > > +#include <dm.h>
> > >  #include <dm/lists.h>
> > >  #include <linux/delay.h>
> > > +#include <dm/root.h>
> > > +#include <dm/device-internal.h>
> >
> > These should go up one line.
> >
> Ok. Will do in next version.
>
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.de
> > nx.de%2Fwiki%2FU-
> > Boot%2FCodingStyle&amp;data=04%7C01%7Cgaurav.jain%40nxp.com%7C021c
> > 004f07e44d796a7408d9c9dc9e41%7C686ea1d3bc2b4c6fa92cd99c5c301635%7
> > C0%7C0%7C637762771646492648%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC
> > 4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&a
> > mp;sdata=HOzWAz8vqKuavYOZopqZf3iLD5dbenfY2UEF%2BO0h1W4%3D&amp;r
> > eserved=0
> >
> > Re the uclass, this is using MISC. What operations are actually supported? I am
> > still not sure why this doesn't deserve its own uclass.
> >
> Ioctl operation(caam_jr_ioctl) provided by MISC Uclass is sufficient for this driver.
> I do not see a need for introducing a new Uclass to support this driver.

OK, well we can go with that for now.

>
> >
> > [..]
> >
> > > diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index
> > > 1047aa772c..c5e5ed5c26 100644
> > > --- a/drivers/crypto/fsl/jr.h
> > > +++ b/drivers/crypto/fsl/jr.h
> > > @@ -1,6 +1,7 @@
> > >  /* SPDX-License-Identifier: GPL-2.0+ */
> > >  /*
> > >   * Copyright 2008-2014 Freescale Semiconductor, Inc.
> > > + * Copyright 2021 NXP
> > >   *
> > >   */
> > >
> > > @@ -8,7 +9,9 @@
> > >  #define __JR_H
> > >
> > >  #include <linux/compiler.h>
> > > +#include "fsl_sec.h"
> > >  #include "type.h"
> > > +#include <misc.h>
> > >
> > >  #define JR_SIZE 4
> > >  /* Timeout currently defined as 10 sec */ @@ -35,12 +38,21 @@
> > >  #define JRSLIODN_SHIFT         0
> > >  #define JRSLIODN_MASK          0x00000fff
> > >
> > > +#define JRDID_MS_PRIM_DID      BIT(0)
> > > +#define JRDID_MS_PRIM_TZ       BIT(4)
> > > +#define JRDID_MS_TZ_OWN                BIT(15)
> > > +
> > >  #define JQ_DEQ_ERR             -1
> > >  #define JQ_DEQ_TO_ERR          -2
> > >  #define JQ_ENQ_ERR             -3
> >
> > Good idea to put brackets around #defines that are a -ve number.
> Will do in next version.
> >
> > >
> > >  #define RNG4_MAX_HANDLES       2
> > >
> > > +enum {
> > > +       /* Run caam jobring descriptor(in buf) */
> > > +       CAAM_JR_RUN_DESC,
> > > +};
> > > +
> > >  struct op_ring {
> > >         caam_dma_addr_t desc;
> > >         uint32_t status;
> > > @@ -102,6 +114,13 @@ struct result {
> > >         uint32_t status;
> > >  };
> > >
> > > +struct caam_regs {
> > > +       ccsr_sec_t *sec;
> > > +       struct jr_regs *regs;
> > > +       u8 jrid;
> > > +       struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
> > > +};
> >
> > Don't forget to comment the structs.
> Will add in next version.
>
> > > +
> > >  void caam_jr_strstatus(u32 status);
> > >  int run_descriptor_jr(uint32_t *desc);
> >
> > and exported functions (normally drivers shouldn't have these).
> Yes I agree. Since run_descriptor_jr() is already in use.
> I am planning a separate patch to move other user of run_descriptor_jr() to caam_jr_ioctl().

OK. But that alone might indicate a new uclass would be generally
useful. Anyway, this is fine and it can be considered later.

Regards,
Simon
diff mbox series

Patch

diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 22b649219e..441550f348 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -1,7 +1,7 @@ 
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  *
  * Based on CAAM driver in drivers/crypto/caam in Linux
  */
@@ -11,7 +11,6 @@ 
 #include <linux/kernel.h>
 #include <log.h>
 #include <malloc.h>
-#include "fsl_sec.h"
 #include "jr.h"
 #include "jobdesc.h"
 #include "desc_constr.h"
@@ -21,8 +20,11 @@ 
 #include <asm/cache.h>
 #include <asm/fsl_pamu.h>
 #endif
+#include <dm.h>
 #include <dm/lists.h>
 #include <linux/delay.h>
+#include <dm/root.h>
+#include <dm/device-internal.h>
 
 #define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size - 1))
 #define CIRC_SPACE(head, tail, size)	CIRC_CNT((tail), (head) + 1, (size))
@@ -35,20 +37,29 @@  uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
 #endif
 };
 
+#if CONFIG_IS_ENABLED(DM)
+struct udevice *caam_dev;
+#else
 #define SEC_ADDR(idx)	\
 	(ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
 
 #define SEC_JR0_ADDR(idx)	\
 	(ulong)(SEC_ADDR(idx) +	\
 	 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+struct caam_regs caam_st;
+#endif
 
-struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+static inline u32 jr_start_reg(u8 jrid)
+{
+	return (1 << jrid);
+}
 
-static inline void start_jr0(uint8_t sec_idx)
+static inline void start_jr(struct caam_regs *caam)
 {
-	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+	ccsr_sec_t *sec = caam->sec;
 	u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
 	u32 scfgr = sec_in32(&sec->scfgr);
+	u32 jrstart = jr_start_reg(caam->jrid);
 
 	if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
 		/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
@@ -56,23 +67,16 @@  static inline void start_jr0(uint8_t sec_idx)
 		 */
 		if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
 		    (scfgr & SEC_SCFGR_VIRT_EN))
-			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+			sec_out32(&sec->jrstartr, jrstart);
 	} else {
 		/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
 		if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
-			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+			sec_out32(&sec->jrstartr, jrstart);
 	}
 }
 
-static inline void jr_reset_liodn(uint8_t sec_idx)
+static inline void jr_disable_irq(struct jr_regs *regs)
 {
-	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
-	sec_out32(&sec->jrliodnr[0].ls, 0);
-}
-
-static inline void jr_disable_irq(uint8_t sec_idx)
-{
-	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
 	uint32_t jrcfg = sec_in32(&regs->jrcfg1);
 
 	jrcfg = jrcfg | JR_INTMASK;
@@ -80,10 +84,10 @@  static inline void jr_disable_irq(uint8_t sec_idx)
 	sec_out32(&regs->jrcfg1, jrcfg);
 }
 
-static void jr_initregs(uint8_t sec_idx)
+static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
 {
-	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
-	struct jobring *jr = &jr0[sec_idx];
+	struct jr_regs *regs = caam->regs;
+	struct jobring *jr = &caam->jr[sec_idx];
 	caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
 	caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
 
@@ -103,16 +107,16 @@  static void jr_initregs(uint8_t sec_idx)
 	sec_out32(&regs->irs, JR_SIZE);
 
 	if (!jr->irq)
-		jr_disable_irq(sec_idx);
+		jr_disable_irq(regs);
 }
 
-static int jr_init(uint8_t sec_idx)
+static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
 {
-	struct jobring *jr = &jr0[sec_idx];
+	struct jobring *jr = &caam->jr[sec_idx];
 
 	memset(jr, 0, sizeof(struct jobring));
 
-	jr->jq_id = DEFAULT_JR_ID;
+	jr->jq_id = caam->jrid;
 	jr->irq = DEFAULT_IRQ;
 
 #ifdef CONFIG_FSL_CORENET
@@ -134,53 +138,8 @@  static int jr_init(uint8_t sec_idx)
 	memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
 	memset(jr->output_ring, 0, jr->op_size);
 
-	start_jr0(sec_idx);
-
-	jr_initregs(sec_idx);
-
-	return 0;
-}
-
-static int jr_sw_cleanup(uint8_t sec_idx)
-{
-	struct jobring *jr = &jr0[sec_idx];
-
-	jr->head = 0;
-	jr->tail = 0;
-	jr->read_idx = 0;
-	jr->write_idx = 0;
-	memset(jr->info, 0, sizeof(jr->info));
-	memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
-	memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
-
-	return 0;
-}
-
-static int jr_hw_reset(uint8_t sec_idx)
-{
-	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
-	uint32_t timeout = 100000;
-	uint32_t jrint, jrcr;
-
-	sec_out32(&regs->jrcr, JRCR_RESET);
-	do {
-		jrint = sec_in32(&regs->jrint);
-	} while (((jrint & JRINT_ERR_HALT_MASK) ==
-		  JRINT_ERR_HALT_INPROGRESS) && --timeout);
-
-	jrint = sec_in32(&regs->jrint);
-	if (((jrint & JRINT_ERR_HALT_MASK) !=
-	     JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
-		return -1;
-
-	timeout = 100000;
-	sec_out32(&regs->jrcr, JRCR_RESET);
-	do {
-		jrcr = sec_in32(&regs->jrcr);
-	} while ((jrcr & JRCR_RESET) && --timeout);
-
-	if (timeout == 0)
-		return -1;
+	start_jr(caam);
+	jr_initregs(sec_idx, caam);
 
 	return 0;
 }
@@ -188,10 +147,10 @@  static int jr_hw_reset(uint8_t sec_idx)
 /* -1 --- error, can't enqueue -- no space available */
 static int jr_enqueue(uint32_t *desc_addr,
 	       void (*callback)(uint32_t status, void *arg),
-	       void *arg, uint8_t sec_idx)
+	       void *arg, uint8_t sec_idx, struct caam_regs *caam)
 {
-	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
-	struct jobring *jr = &jr0[sec_idx];
+	struct jr_regs *regs = caam->regs;
+	struct jobring *jr = &caam->jr[sec_idx];
 	int head = jr->head;
 	uint32_t desc_word;
 	int length = desc_len(desc_addr);
@@ -263,10 +222,10 @@  static int jr_enqueue(uint32_t *desc_addr,
 	return 0;
 }
 
-static int jr_dequeue(int sec_idx)
+static int jr_dequeue(int sec_idx, struct caam_regs *caam)
 {
-	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
-	struct jobring *jr = &jr0[sec_idx];
+	struct jr_regs *regs = caam->regs;
+	struct jobring *jr = &caam->jr[sec_idx];
 	int head = jr->head;
 	int tail = jr->tail;
 	int idx, i, found;
@@ -349,14 +308,18 @@  static void desc_done(uint32_t status, void *arg)
 {
 	struct result *x = arg;
 	x->status = status;
-#ifndef CONFIG_SPL_BUILD
 	caam_jr_strstatus(status);
-#endif
 	x->done = 1;
 }
 
 static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
 {
+	struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+	caam = dev_get_priv(caam_dev);
+#else
+	caam = &caam_st;
+#endif
 	unsigned long long timeval = 0;
 	unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
 	struct result op;
@@ -364,7 +327,7 @@  static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
 
 	memset(&op, 0, sizeof(op));
 
-	ret = jr_enqueue(desc, desc_done, &op, sec_idx);
+	ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
 	if (ret) {
 		debug("Error in SEC enq\n");
 		ret = JQ_ENQ_ERR;
@@ -375,7 +338,7 @@  static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
 		udelay(1);
 		timeval += 1;
 
-		ret = jr_dequeue(sec_idx);
+		ret = jr_dequeue(sec_idx, caam);
 		if (ret) {
 			debug("Error in SEC deq\n");
 			ret = JQ_DEQ_ERR;
@@ -402,13 +365,62 @@  int run_descriptor_jr(uint32_t *desc)
 	return run_descriptor_jr_idx(desc, 0);
 }
 
+static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam)
+{
+	struct jobring *jr = &caam->jr[sec_idx];
+
+	jr->head = 0;
+	jr->tail = 0;
+	jr->read_idx = 0;
+	jr->write_idx = 0;
+	memset(jr->info, 0, sizeof(jr->info));
+	memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
+	memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
+
+	return 0;
+}
+
+static int jr_hw_reset(struct jr_regs *regs)
+{
+	uint32_t timeout = 100000;
+	uint32_t jrint, jrcr;
+
+	sec_out32(&regs->jrcr, JRCR_RESET);
+	do {
+		jrint = sec_in32(&regs->jrint);
+	} while (((jrint & JRINT_ERR_HALT_MASK) ==
+		  JRINT_ERR_HALT_INPROGRESS) && --timeout);
+
+	jrint = sec_in32(&regs->jrint);
+	if (((jrint & JRINT_ERR_HALT_MASK) !=
+	     JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
+		return -1;
+
+	timeout = 100000;
+	sec_out32(&regs->jrcr, JRCR_RESET);
+	do {
+		jrcr = sec_in32(&regs->jrcr);
+	} while ((jrcr & JRCR_RESET) && --timeout);
+
+	if (timeout == 0)
+		return -1;
+
+	return 0;
+}
+
 static inline int jr_reset_sec(uint8_t sec_idx)
 {
-	if (jr_hw_reset(sec_idx) < 0)
+	struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+	caam = dev_get_priv(caam_dev);
+#else
+	caam = &caam_st;
+#endif
+	if (jr_hw_reset(caam->regs) < 0)
 		return -1;
 
 	/* Clean up the jobring structure maintained by software */
-	jr_sw_cleanup(sec_idx);
+	jr_sw_cleanup(sec_idx, caam);
 
 	return 0;
 }
@@ -418,9 +430,15 @@  int jr_reset(void)
 	return jr_reset_sec(0);
 }
 
-static inline int sec_reset_idx(uint8_t sec_idx)
+int sec_reset(void)
 {
-	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+	struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+	caam = dev_get_priv(caam_dev);
+#else
+	caam = &caam_st;
+#endif
+	ccsr_sec_t *sec = caam->sec;
 	uint32_t mcfgr = sec_in32(&sec->mcfgr);
 	uint32_t timeout = 100000;
 
@@ -446,11 +464,7 @@  static inline int sec_reset_idx(uint8_t sec_idx)
 
 	return 0;
 }
-int sec_reset(void)
-{
-	return sec_reset_idx(0);
-}
-#ifndef CONFIG_SPL_BUILD
+
 static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
 {
 	u32 *desc;
@@ -496,12 +510,11 @@  static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
 	return ret;
 }
 
-static int instantiate_rng(u8 sec_idx, int gen_sk)
+static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int gen_sk)
 {
 	u32 *desc;
 	u32 rdsta_val;
 	int ret = 0, sh_idx, size;
-	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 
@@ -554,9 +567,8 @@  static int instantiate_rng(u8 sec_idx, int gen_sk)
 	return ret;
 }
 
-static u8 get_rng_vid(uint8_t sec_idx)
+static u8 get_rng_vid(ccsr_sec_t *sec)
 {
-	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	u8 vid;
 
 	if (caam_get_era() < 10) {
@@ -574,9 +586,8 @@  static u8 get_rng_vid(uint8_t sec_idx)
  * By default, the TRNG runs for 200 clocks per sample;
  * 1200 clocks per sample generates better entropy.
  */
-static void kick_trng(int ent_delay, uint8_t sec_idx)
+static void kick_trng(int ent_delay, ccsr_sec_t *sec)
 {
-	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 	u32 val;
@@ -603,10 +614,9 @@  static void kick_trng(int ent_delay, uint8_t sec_idx)
 	sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
 }
 
-static int rng_init(uint8_t sec_idx)
+static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
 {
 	int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
-	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 	u32 inst_handles;
@@ -624,7 +634,7 @@  static int rng_init(uint8_t sec_idx)
 		 * the TRNG parameters.
 		 */
 		if (!inst_handles) {
-			kick_trng(ent_delay, sec_idx);
+			kick_trng(ent_delay, sec);
 			ent_delay += 400;
 		}
 		/*
@@ -634,7 +644,7 @@  static int rng_init(uint8_t sec_idx)
 		 * interval, leading to a sucessful initialization of
 		 * the RNG.
 		 */
-		ret = instantiate_rng(sec_idx, gen_sk);
+		ret = instantiate_rng(sec_idx, sec, gen_sk);
 	} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 	if (ret) {
 		printf("SEC%u:  Failed to instantiate RNG\n", sec_idx);
@@ -646,13 +656,28 @@  static int rng_init(uint8_t sec_idx)
 
 	return ret;
 }
-#endif
+
 int sec_init_idx(uint8_t sec_idx)
 {
-	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
-	uint32_t mcr = sec_in32(&sec->mcfgr);
 	int ret = 0;
-
+	struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+	if (!caam_dev) {
+		printf("caam_jr: caam not found\n");
+		return -1;
+	}
+	caam = dev_get_priv(caam_dev);
+#else
+	caam_st.sec = (void *)SEC_ADDR(sec_idx);
+	caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+	caam_st.jrid = 0;
+	caam = &caam_st;
+#endif
+	ccsr_sec_t *sec = caam->sec;
+	uint32_t mcr = sec_in32(&sec->mcfgr);
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+	uint32_t jrdid_ms = 0;
+#endif
 #ifdef CONFIG_FSL_CORENET
 	uint32_t liodnr;
 	uint32_t liodn_ns;
@@ -682,6 +707,11 @@  int sec_init_idx(uint8_t sec_idx)
 	mcr |= (1 << MCFGR_PS_SHIFT);
 #endif
 	sec_out32(&sec->mcfgr, mcr);
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+	jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID;
+	sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms);
+#endif
+	jr_reset();
 
 #ifdef CONFIG_FSL_CORENET
 #ifdef CONFIG_SPL_BUILD
@@ -693,20 +723,19 @@  int sec_init_idx(uint8_t sec_idx)
 	liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
 	liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
 
-	liodnr = sec_in32(&sec->jrliodnr[0].ls) &
+	liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
 		 ~(JRNSLIODN_MASK | JRSLIODN_MASK);
 	liodnr = liodnr |
 		 (liodn_ns << JRNSLIODN_SHIFT) |
 		 (liodn_s << JRSLIODN_SHIFT);
-	sec_out32(&sec->jrliodnr[0].ls, liodnr);
+	sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
 #else
-	liodnr = sec_in32(&sec->jrliodnr[0].ls);
+	liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
 	liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
 	liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
 #endif
 #endif
-
-	ret = jr_init(sec_idx);
+	ret = jr_init(sec_idx, caam);
 	if (ret < 0) {
 		printf("SEC%u:  initialization failed\n", sec_idx);
 		return -1;
@@ -719,9 +748,9 @@  int sec_init_idx(uint8_t sec_idx)
 
 	pamu_enable();
 #endif
-#ifndef CONFIG_SPL_BUILD
-	if (get_rng_vid(sec_idx) >= 4) {
-		if (rng_init(sec_idx) < 0) {
+
+	if (get_rng_vid(caam->sec) >= 4) {
+		if (rng_init(sec_idx, caam->sec) < 0) {
 			printf("SEC%u:  RNG instantiation failed\n", sec_idx);
 			return -1;
 		}
@@ -735,7 +764,6 @@  int sec_init_idx(uint8_t sec_idx)
 
 		printf("SEC%u:  RNG instantiated\n", sec_idx);
 	}
-#endif
 	return ret;
 }
 
@@ -743,3 +771,76 @@  int sec_init(void)
 {
 	return sec_init_idx(0);
 }
+
+#if CONFIG_IS_ENABLED(DM)
+static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
+{
+	if (request != CAAM_JR_RUN_DESC)
+		return -ENOSYS;
+
+	return run_descriptor_jr(buf);
+}
+
+static int caam_jr_probe(struct udevice *dev)
+{
+	struct caam_regs *caam = dev_get_priv(dev);
+	fdt_addr_t addr;
+	ofnode node;
+	unsigned int jr_node = 0;
+
+	caam_dev = dev;
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
+		printf("caam_jr: crypto not found\n");
+		return -EINVAL;
+	}
+	caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
+	caam->regs = (struct jr_regs *)caam->sec;
+
+	/* Check for enabled job ring node */
+	ofnode_for_each_subnode(node, dev_ofnode(dev)) {
+		if (!ofnode_is_available(node))
+			continue;
+
+		jr_node = ofnode_read_u32_default(node, "reg", -1);
+		if (jr_node > 0) {
+			caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
+			while (!(jr_node & 0x0F))
+				jr_node = jr_node >> 4;
+
+			caam->jrid = jr_node - 1;
+			break;
+		}
+	}
+
+	if (sec_init())
+		printf("\nsec_init failed!\n");
+
+	return 0;
+}
+
+static int caam_jr_bind(struct udevice *dev)
+{
+	return 0;
+}
+
+static const struct misc_ops caam_jr_ops = {
+	.ioctl = caam_jr_ioctl,
+};
+
+static const struct udevice_id caam_jr_match[] = {
+	{ .compatible = "fsl,sec-v4.0" },
+	{ }
+};
+
+U_BOOT_DRIVER(caam_jr) = {
+	.name		= "caam_jr",
+	.id		= UCLASS_MISC,
+	.of_match	= caam_jr_match,
+	.ops		= &caam_jr_ops,
+	.bind		= caam_jr_bind,
+	.probe		= caam_jr_probe,
+	.priv_auto	= sizeof(struct caam_regs),
+};
+#endif
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 1047aa772c..c5e5ed5c26 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -1,6 +1,7 @@ 
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  *
  */
 
@@ -8,7 +9,9 @@ 
 #define __JR_H
 
 #include <linux/compiler.h>
+#include "fsl_sec.h"
 #include "type.h"
+#include <misc.h>
 
 #define JR_SIZE 4
 /* Timeout currently defined as 10 sec */
@@ -35,12 +38,21 @@ 
 #define JRSLIODN_SHIFT		0
 #define JRSLIODN_MASK		0x00000fff
 
+#define JRDID_MS_PRIM_DID	BIT(0)
+#define JRDID_MS_PRIM_TZ	BIT(4)
+#define JRDID_MS_TZ_OWN		BIT(15)
+
 #define JQ_DEQ_ERR		-1
 #define JQ_DEQ_TO_ERR		-2
 #define JQ_ENQ_ERR		-3
 
 #define RNG4_MAX_HANDLES	2
 
+enum {
+	/* Run caam jobring descriptor(in buf) */
+	CAAM_JR_RUN_DESC,
+};
+
 struct op_ring {
 	caam_dma_addr_t desc;
 	uint32_t status;
@@ -102,6 +114,13 @@  struct result {
 	uint32_t status;
 };
 
+struct caam_regs {
+	ccsr_sec_t *sec;
+	struct jr_regs *regs;
+	u8 jrid;
+	struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+};
+
 void caam_jr_strstatus(u32 status);
 int run_descriptor_jr(uint32_t *desc);