diff mbox series

ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board

Message ID 20211128025318.367051-1-marex@denx.de
State Accepted
Commit ca27227c5940371c792cfd36826315b3e17e46a1
Delegated to: Stefano Babic
Headers show
Series ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board | expand

Commit Message

Marek Vasut Nov. 28, 2021, 2:53 a.m. UTC 
From: Christoph Niedermaier <cniedermaier@dh-electronics.com>

The PDK2 board is capable of running both 100M and 1G ethernet. However,
the i.MX6 has only one ethernet MAC, so it is possible to configure
either 100M or 1G Ethernet. In case of 100M option, the PHY is on the
SoM and the signals are routed to a RJ45 port. For 1G the PHY is on
the PDK2 board with another RJ45 port. 100M and 1G ethernet use
different signal pins from the i.MX6, but share the MDIO bus.

This SoM board combination is used to demonstrate how to enable 1G
ethernet configuration.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
---
NOTE: Adapted from Linux 298591bf725a ("ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board")
---
 arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi |  2 +-
 arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi        | 50 +++++++++++++++++++--
 include/configs/dh_imx6.h                   |  4 +-
 3 files changed, 50 insertions(+), 6 deletions(-)

Comments

Stefano Babic Feb. 5, 2022, 4:43 p.m. UTC | #1 
> From: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> The PDK2 board is capable of running both 100M and 1G ethernet. However,
> the i.MX6 has only one ethernet MAC, so it is possible to configure
> either 100M or 1G Ethernet. In case of 100M option, the PHY is on the
> SoM and the signals are routed to a RJ45 port. For 1G the PHY is on
> the PDK2 board with another RJ45 port. 100M and 1G ethernet use
> different signal pins from the i.MX6, but share the MDIO bus.
> This SoM board combination is used to demonstrate how to enable 1G
> ethernet configuration.
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Cc: Stefano Babic <sbabic@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic
diff mbox series

Patch

diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi
index 32128d4d2ab..a1ffb1d6fc5 100644
--- a/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-dhcom-pdk2-u-boot.dtsi
@@ -15,7 +15,7 @@ 
 };
 
 &fec {
-	phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <1>;
 	phy-reset-post-delay = <10>;
 
diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi
index af4719aaeba..d8772a98966 100644
--- a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi
+++ b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi
@@ -38,6 +38,45 @@ 
 	status = "okay";
 };
 
+/* 1G ethernet */
+/delete-node/ &ethphy0;
+&fec {
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy7>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet_1G>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy7: ethernet-phy@7 { /* KSZ 9021 */
+			compatible = "ethernet-phy-ieee802.3-c22";
+			interrupt-parent = <&gpio1>;
+			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+			pinctrl-0 = <&pinctrl_ethphy7>;
+			pinctrl-names = "default";
+			reg = <7>;
+			reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <1000>;
+			reset-deassert-us = <1000>;
+			rxc-skew-ps = <3000>;
+			rxd0-skew-ps = <0>;
+			rxd1-skew-ps = <0>;
+			rxd2-skew-ps = <0>;
+			rxd3-skew-ps = <0>;
+			txc-skew-ps = <3000>;
+			txd0-skew-ps = <0>;
+			txd1-skew-ps = <0>;
+			txd2-skew-ps = <0>;
+			txd3-skew-ps = <0>;
+			rxdv-skew-ps = <0>;
+			txen-skew-ps = <0>;
+		};
+	};
+};
+
 &hdmi {
 	ddc-i2c-bus = <&i2c2>;
 	status = "okay";
@@ -113,9 +152,14 @@ 
 			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
 			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
 			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x000b0
-			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x000b1
-			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0x000b1
+		>;
+	};
+
+	pinctrl_ethphy7: ethphy7-grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0xb0 /* Reset */
+			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0xb1 /* Int */
+			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0xb1 /* WOL */
 		>;
 	};
 
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 8183e7debd4..3cf0578b5e1 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -32,9 +32,9 @@ 
 
 /* FEC ethernet */
 #define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_FEC_XCV_TYPE		RGMII
 #define CONFIG_ETHPRIME			"FEC"
-#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_FEC_MXC_PHYADDR		7
 #define CONFIG_ARP_TIMEOUT		200UL
 
 /* MMC Configs */