diff mbox series

Convert CONFIG_FSL_DDR_BIST et al to Kconfig

Message ID 20211114002243.1840490-1-trini@konsulko.com
State Accepted
Commit 33b02e93ecb3f6e3f128618e129785f3fdeb3cd9
Delegated to: Tom Rini
Headers show
Series Convert CONFIG_FSL_DDR_BIST et al to Kconfig | expand

Commit Message

Tom Rini Nov. 14, 2021, 12:22 a.m. UTC 
This converts the following to Kconfig:
   CONFIG_FSL_DDR_BIST
   CONFIG_FSL_DDR_INTERACTIVE

Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++++
 include/configs/lx2160a_common.h          | 2 --
 2 files changed, 4 insertions(+), 2 deletions(-)

Comments

Tom Rini Dec. 1, 2021, 6:32 p.m. UTC | #1 
On Sat, Nov 13, 2021 at 07:22:43PM -0500, Tom Rini wrote:

> This converts the following to Kconfig:
>    CONFIG_FSL_DDR_BIST
>    CONFIG_FSL_DDR_INTERACTIVE
> 
> Signed-off-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/next, thanks!
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 1a057f7059b7..a6ac897ab307 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -233,6 +233,8 @@  config ARCH_LS2080A
 config ARCH_LX2162A
 	bool
 	select ARMV8_SET_SMPEN
+	select FSL_DDR_BIST
+	select FSL_DDR_INTERACTIVE
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
 	select GICV3
@@ -267,6 +269,8 @@  config ARCH_LX2162A
 config ARCH_LX2160A
 	bool
 	select ARMV8_SET_SMPEN
+	select FSL_DDR_BIST
+	select FSL_DDR_INTERACTIVE
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
 	select GICV3
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 7173fe6ba656..0710004776ea 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -18,7 +18,6 @@ 
 #define CONFIG_SYS_FLASH_BASE		0x20000000
 
 /* DDR */
-#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
 #define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE		0x80000000UL
@@ -38,7 +37,6 @@ 
 #define CONFIG_SYS_SPD_BUS_NUM		0	/* SPD on I2C bus 0 */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
-#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
 #define CONFIG_SYS_MONITOR_LEN		(936 * 1024)
 
 /* Miscellaneous configurable options */