Message ID | 20211107150856.19256-1-sin.hui.kho@intel.com |
---|---|
State | Accepted |
Commit | 2f27754eb7f5321b9e4ff80870f03e35357a02a5 |
Delegated to: | Simon Goldschmidt |
Headers | show |
Series | [1/3] arm: socfpga: arria10: Setting image magic value to romcode initswstate reg | expand |
> -----Original Message----- > From: Kho, Sin Hui <sin.hui.kho@intel.com> > Sent: Sunday, 7 November, 2021 11:09 PM > To: u-boot@lists.denx.de > Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Marek Vasut > <marex@denx.de>; Chee, Tien Fong <tien.fong.chee@intel.com>; Hea, Kok > Kiang <kok.kiang.hea@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Cozart, Sue <sue.cozart@intel.com>; Kho, Sin > Hui <sin.hui.kho@intel.com> > Subject: [PATCH 1/3] arm: socfpga: arria10: Setting image magic value to > romcode initswstate reg > > From: Tien Fong Chee <tien.fong.chee@intel.com> > > The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID > value if the current FSBL image is found valid, otherwise BootROM will look for > next subsequent valid FSBL image when warm reset is triggered. > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> > Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> > --- > .../mach-socfpga/include/mach/system_manager_arria10.h | 3 ++- > arch/arm/mach-socfpga/spl_a10.c | 10 +++++++++- > 2 files changed, 11 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h > b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h > index e4fc6d2e55..75e1fcd80f 100644 > --- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h > @@ -1,6 +1,6 @@ > /* SPDX-License-Identifier: GPL-2.0 */ > /* > - * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> > + * Copyright (C) 2016-2021 Intel Corporation <www.intel.com> > */ > > #ifndef _SYSTEM_MANAGER_ARRIA10_H_ > @@ -31,6 +31,7 @@ > #define SYSMGR_A10_NOC_IDLEACK 0xd0 > #define SYSMGR_A10_NOC_IDLESTATUS 0xd4 > #define SYSMGR_A10_FPGA2SOC_CTRL 0xd8 > +#define SYSMGR_A10_ROMCODE_INITSWSTATE 0x20C > > #define SYSMGR_SDMMC SYSMGR_A10_SDMMC > > diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach- > socfpga/spl_a10.c index ecb656e4de..f6c4b5708d 100644 > --- a/arch/arm/mach-socfpga/spl_a10.c > +++ b/arch/arm/mach-socfpga/spl_a10.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0+ > /* > - * Copyright (C) 2012-2019 Altera Corporation <www.altera.com> > + * Copyright (C) 2012-2021 Altera Corporation <www.altera.com> > */ > > #include <common.h> > @@ -32,6 +32,7 @@ > #include <memalign.h> > > #define FPGA_BUFSIZ 16 * 1024 > +#define FSBL_IMAGE_IS_VALID 0x49535756 > > DECLARE_GLOBAL_DATA_PTR; > > @@ -169,3 +170,10 @@ void board_init_f(ulong dummy) > config_dedicated_pins(gd->fdt_blob); > WATCHDOG_RESET(); > } > + > +/* board specific function prior loading SSBL / U-Boot proper */ void > +spl_board_prepare_for_boot(void) { > + writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() + > + SYSMGR_A10_ROMCODE_INITSWSTATE); } > -- > 2.25.1 Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h index e4fc6d2e55..75e1fcd80f 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2021 Intel Corporation <www.intel.com> */ #ifndef _SYSTEM_MANAGER_ARRIA10_H_ @@ -31,6 +31,7 @@ #define SYSMGR_A10_NOC_IDLEACK 0xd0 #define SYSMGR_A10_NOC_IDLESTATUS 0xd4 #define SYSMGR_A10_FPGA2SOC_CTRL 0xd8 +#define SYSMGR_A10_ROMCODE_INITSWSTATE 0x20C #define SYSMGR_SDMMC SYSMGR_A10_SDMMC diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index ecb656e4de..f6c4b5708d 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012-2019 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2021 Altera Corporation <www.altera.com> */ #include <common.h> @@ -32,6 +32,7 @@ #include <memalign.h> #define FPGA_BUFSIZ 16 * 1024 +#define FSBL_IMAGE_IS_VALID 0x49535756 DECLARE_GLOBAL_DATA_PTR; @@ -169,3 +170,10 @@ void board_init_f(ulong dummy) config_dedicated_pins(gd->fdt_blob); WATCHDOG_RESET(); } + +/* board specific function prior loading SSBL / U-Boot proper */ +void spl_board_prepare_for_boot(void) +{ + writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() + + SYSMGR_A10_ROMCODE_INITSWSTATE); +}