From patchwork Fri Oct 22 22:19:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 1545119 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4Hbf1T3B7Vz9sRN for ; Sat, 23 Oct 2021 09:20:29 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6644A83535; Sat, 23 Oct 2021 00:20:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ziswiler.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id E9F3E834F4; Sat, 23 Oct 2021 00:19:56 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4F461831D3 for ; Sat, 23 Oct 2021 00:19:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=ziswiler.com Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=marcel@ziswiler.com Received: from toolbox.cardiotech.int ([194.191.235.54]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1N5FYf-1mnqWt3gov-011D8J; Sat, 23 Oct 2021 00:19:39 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Cc: Michael Walle , Frieder Schrempf , Fabio Estevam , Marcel Ziswiler , Priyanka Jain Subject: [PATCH v4 4/5] doc: board: kontron: sl28: Reduce section levels and change title Date: Sat, 23 Oct 2021 00:19:23 +0200 Message-Id: <20211022221924.1226010-5-marcel@ziswiler.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20211022221924.1226010-1-marcel@ziswiler.com> References: <20211022221924.1226010-1-marcel@ziswiler.com> MIME-Version: 1.0 X-Provags-ID: V03:K1:0QZoPJVdD9eMHxckF3wjehNlXM8L+0f/pbtSdQtqJh3asrk1pPo GitOhNj44bgoqiFkrCOsjQeO/UUgHAukMDz6T6qED/ekXHoh+CM4z215UmwwcST4KbsPOVG uNiPMMkldc+45r5nrtpCHMiq8W11af4kJBUeREY1FwLX+jLQbHQiKXQRZbkBXV/qmKbnoIs Iu5njq7pngd+dbuRavBiw== X-UI-Out-Filterresults: notjunk:1;V03:K0:1RIAMv+fS18=:xYdqIzftUi+j9UefAh7QDu aJ7ee0FJYBLiWO+p07z22GBMjXcGOEpfdHmQRfHvwbjL/xn+FLY3bVT++bcDYNO6cEVpAZME3 OjCl0xfWS/spBE2Kqj8Kw95NnfDuQmjTh8t4Q+kal5FHQfUFFPmiw7YnIihBkr7VI88szXQbz qrznb8ADkE8LFKxYv1f3r0yJbCj8mINpxJF+3pRq6JE+gnvRvbgkhLtGxIc4n9d1Yac4egD+V ldMxk3AfKHO+lh+NK02lTIxis7kKi33b8NoR05dIkv3St5uSVvKMqfDraT4UqiuyCN7ZsvIm+ iErBNJXK5a+OM390ErsY1vKotObI8MR5NFNT2DVoVLZlA8Us16puVDFY7kkC5pZrQrWumoIwz GDvz6OxpFq/jWaPBpx6G5LvChpBM10958f3ujEBMmmhaCFQ1iGLxb1irmX/4VbHi7NdF3VU8Y b2hV27kGbSEXPWbIsaqmW0MHekwuCawc6qAIB4y6mKioIPd43lCcz2CaBvj2aLY3MgQw0KznE McvGx/DeN60i//Q/GukOrGltoeukK3YDjBuAJV1QFixVKlTlAp0gcMFnh2d7c4D3InvO0+VTq cogayqhNetdRJUX7iNK+JCjHY+wNEWyybtwkn3kXu/m+9JFGkLrC9dQwumDt88gm9VfYTb8oZ 9Hdmzsi8HUKZkrVlqr0lh1J+UnZHrvIgXJpyvs1tfdrYT7QIfTzlUCPAtIDzAyq1v1hY= X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Frieder Schrempf In order to add other Kontron boards to the docs alongside the existing sl28 board, we need to reduce the levels of the sections and change the title. Cc: Fabio Estevam Signed-off-by: Frieder Schrempf Acked-by: Michael Walle Signed-off-by: Marcel Ziswiler --- From v3 of Michael: Frieder, Fabio, I took the liberty and added this patch to this series, because the next patch depends on it. It wasn't picked up yet in the imx queue. In fact, Frieders patches should not depend on this one, although the documentation will be incorrectly formatted, so it should be fine if this patch will go through the qoriq queue. Changes in v4: - Re-based on top of imx/master. Changes in v3: - none Changes in v2: - new patch doc/board/kontron/sl28.rst | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst index e458fbc607c..07431986d8f 100644 --- a/doc/board/kontron/sl28.rst +++ b/doc/board/kontron/sl28.rst @@ -1,17 +1,17 @@ .. SPDX-License-Identifier: GPL-2.0+ -Summary -======= +Kontron SMARC-sAL28 +=================== The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72 processor module with an on-chip 6-port TSN switch and a 3D GPU. Quickstart -========== +---------- Compile U-Boot --------------- +^^^^^^^^^^^^^^ Configure and compile the binary:: @@ -21,7 +21,7 @@ Configure and compile the binary:: Copy u-boot.rom to a TFTP server. Install the bootloader on the board ------------------------------------ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Please note, this bootloader doesn't support the builtin watchdog (yet), therefore you have to disable it, see below. Otherwise you'll end up in @@ -36,7 +36,7 @@ disabled the builtin watchdog you might have to manually enter failsafe mode by asserting the ``FORCE_RECOV#`` line during board reset. Disable the builtin watchdog ----------------------------- +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - boot into the failsafe bootloader, either by asserting the ``FORCE_RECOV#`` line or if you still have the original bootloader @@ -53,7 +53,7 @@ Disable the builtin watchdog Useful I2C tricks -================= +----------------- The board has a board management controller which is not supported in u-boot (yet). But you can use the i2c command to access it. @@ -68,7 +68,7 @@ u-boot (yet). But you can use the i2c command to access it. Non-volatile Board Configuration Bits -===================================== +------------------------------------- The board has 16 configuration bits which are stored in the CPLD and are non-volatile. These can be changed by the `sl28 nvm` command. @@ -98,21 +98,21 @@ Please note, that if the board is in failsafe mode, the bits will have the factory defaults, ie. all bits are off. Power-On Inhibit ----------------- +^^^^^^^^^^^^^^^^ If this is set, the board doesn't automatically turn on when power is applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or use any other wake-up source such as RTC alarm or Wake-on-LAN. eMMC Boot ---------- +^^^^^^^^^ If this is set, the RCW will be fetched from the on-board eMMC at offset 1MiB. For further details, have a look at the `Reset Configuration Word Documentation`_. Watchdog --------- +^^^^^^^^ By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and 3, the user can change its mode or disable it altogether. @@ -127,21 +127,21 @@ Bit 2 Bit 3 Description ===== ===== =============================== Clock Generator Select ----------------------- +^^^^^^^^^^^^^^^^^^^^^^ The board is prepared to supply different SerDes clock speeds. But for now, only setting 0 is supported, otherwise the CPU will hang because the PLL will not lock. Clock Output Disable And Keep Devices In Reset ----------------------------------------------- +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ To safe power, the user might disable different devices and clock output of the board. It is not supported to disable the "CPU SerDes clock #2" for now, otherwise the CPU will hang because the PLL will not lock. Automatic reset of the onboard PHYs ------------------------------------ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ By default, there is no hardware reset of the onboard PHY. This is because for Wake-on-LAN, some registers have to retain their values. If you don't @@ -151,7 +151,7 @@ power-on reset. Further documentation -===================== +--------------------- - `Vendor Documentation`_ - `Reset Configuration Word Documentation`_