[next,v5,02/12] aspeed: ast2600: Enlarge SRAM size

Message ID	20211004015419.8190-3-chiawei_wang@aspeedtech.com
State	Superseded
Delegated to:	Tom Rini
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Chia-Wei Wang <chiawei_wang@aspeedtech.com> To: <lukma@denx.de>, <trini@konsulko.com>, <sjg@chromium.org>, <u-boot@lists.denx.de> CC: <joel@jms.id.au>, <ryan_chen@aspeedtech.com>, <johnny_huang@aspeedtech.com> Subject: [PATCH next v5 02/12] aspeed: ast2600: Enlarge SRAM size Date: Mon, 4 Oct 2021 09:54:09 +0800 Message-ID: <20211004015419.8190-3-chiawei_wang@aspeedtech.com> In-Reply-To: <20211004015419.8190-1-chiawei_wang@aspeedtech.com> References: <20211004015419.8190-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: list Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	aspeed: Support secure boot chain with FIT image verification \| expand [next,v5,00/12] aspeed: Support secure boot chain with FIT image verification [next,v5,01/12] image: fit: Fix parameter name for hash algorithm [next,v5,02/12] aspeed: ast2600: Enlarge SRAM size [next,v5,03/12] clk: ast2600: Add YCLK control for HACE [next,v5,04/12] crypto: aspeed: Add AST2600 HACE support [next,v5,05/12] ARM: dts: ast2600: Add HACE to device tree [next,v5,06/12] clk: ast2600: Add RSACLK control for ACRY [next,v5,07/12] crypto: aspeed: Add AST2600 ACRY support [next,v5,08/12] ARM: dts: ast2600: Add ACRY to device tree [next,v5,09/12] ast2600: spl: Locate load buffer in DRAM space [next,v5,10/12] configs: ast2600-evb: Enable SPL FIT support [next,v5,11/12] configs: aspeed: Make EXTRA_ENV_SETTINGS board specific [next,v5,12/12] configs: ast2600: Boot kernel FIT in DRAM

Message ID

20211004015419.8190-3-chiawei_wang@aspeedtech.com

State

Superseded

Delegated to:

Tom Rini

Headers

From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <lukma@denx.de>, <trini@konsulko.com>, <sjg@chromium.org>,
 <u-boot@lists.denx.de>
CC: <joel@jms.id.au>, <ryan_chen@aspeedtech.com>,
 <johnny_huang@aspeedtech.com>
Subject: [PATCH next v5 02/12] aspeed: ast2600: Enlarge SRAM size
Date: Mon, 4 Oct 2021 09:54:09 +0800
Message-ID: <20211004015419.8190-3-chiawei_wang@aspeedtech.com>
In-Reply-To: <20211004015419.8190-1-chiawei_wang@aspeedtech.com>
References: <20211004015419.8190-1-chiawei_wang@aspeedtech.com>
MIME-Version: 1.0
Content-Type: text/plain
Precedence: list
Errors-To: u-boot-bounces@lists.denx.de
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

aspeed: Support secure boot chain with FIT image verification | expand

Commit Message

ChiaWei Wang Oct. 4, 2021, 1:54 a.m. UTC

The AST2600 SRAM has been extended to 88KB since A1
chip revision. This patch updates the SRAM size to
offer more space for early stack/heap use.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
 arch/arm/include/asm/arch-aspeed/platform.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h
index d50ec5f8a9..589abd4a3f 100644
--- a/arch/arm/include/asm/arch-aspeed/platform.h
+++ b/arch/arm/include/asm/arch-aspeed/platform.h
@@ -17,7 +17,7 @@ 
 #define ASPEED_MAC_COUNT	4
 #define ASPEED_DRAM_BASE	0x80000000
 #define ASPEED_SRAM_BASE	0x10000000
-#define ASPEED_SRAM_SIZE	0x10000
+#define ASPEED_SRAM_SIZE	0x16000
 #else
 #err "Unrecognized Aspeed platform."
 #endif

[next,v5,02/12] aspeed: ast2600: Enlarge SRAM size

Commit Message

Patch