[v4,2/4] riscv: lib: implement enable_caches for sifive cache

The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.

In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.

Signed-off-by: Zong Li <zong.li@sifive.com>
---
 arch/riscv/Kconfig            |  5 +++++
 arch/riscv/lib/Makefile       |  1 +
 arch/riscv/lib/sifive_cache.c | 27 +++++++++++++++++++++++++++
 common/board_r.c              |  4 ++--
 4 files changed, 35 insertions(+), 2 deletions(-)
 create mode 100644 arch/riscv/lib/sifive_cache.c

> From: Zong Li <zong.li@sifive.com>
> Sent: Tuesday, August 31, 2021 5:21 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; bmeng.cn@gmail.com; seanga2@gmail.com; green.wan@sifive.com; paul.walmsley@sifive.com; sjg@chromium.org; u-boot@lists.denx.de
> Cc: Zong Li <zong.li@sifive.com>
> Subject: [PATCH v4 2/4] riscv: lib: implement enable_caches for sifive cache
>
> The enable_caches is a generic hook for architecture-implemented, we define this function to enable composable cache of sifive platforms.
>
> In sifive_cache, it invokes the generic cache_enable interface of cache uclass to execute the relative implementation in SiFive ccache driver.
>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>  arch/riscv/Kconfig            |  5 +++++
>  arch/riscv/lib/Makefile       |  1 +
>  arch/riscv/lib/sifive_cache.c | 27 +++++++++++++++++++++++++++
>  common/board_r.c              |  4 ++--
>  4 files changed, 35 insertions(+), 2 deletions(-)  create mode 100644 arch/riscv/lib/sifive_cache.c
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4b0c3dffa6..ec651fe0a4 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
>           The SiFive CLINT block holds memory-mapped control and status registers
>           associated with software and timer interrupts.
>
> +config SIFIVE_CACHE
> +       bool
> +       help
> +         This enables the operations to configure SiFive cache
> +
>  config ANDES_PLIC
>         bool
>         depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index c4cc41434b..06020fcc2a 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
>  obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
>  obj-$(CONFIG_CMD_GO) += boot.o
>  obj-y  += cache.o
> +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
>  ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
>  obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
>  obj-$(CONFIG_ANDES_PLIC) += andes_plic.o diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c new file mode 100644 index 0000000000..28154878fc
> --- /dev/null
> +++ b/arch/riscv/lib/sifive_cache.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2021 SiFive, Inc
> + */
> +
> +#include <common.h>
> +#include <cache.h>
> +#include <cpu_func.h>
> +#include <dm.h>
> +
> +void enable_caches(void)
> +{
> +       struct udevice *dev;
> +       int ret;
> +
> +       /* Enable ways of ccache */
> +       ret = uclass_get_device_by_driver(UCLASS_CACHE,
> +                                         DM_DRIVER_GET(sifive_ccache),
> +                                         &dev);
> +       if (ret) {
> +               log_debug("Cannot enable cache ways");
> +       } else {
> +               ret = cache_enable(dev);
> +               if (ret)
> +                       log_debug("ccache enable failed");
> +       }
> +}
> diff --git a/common/board_r.c b/common/board_r.c index e3e6248a1f..630c2451a2 100644
> --- a/common/board_r.c
> +++ b/common/board_r.c
> @@ -114,7 +114,7 @@ static int initr_reloc(void)
>         return 0;
>  }
>
> -#ifdef CONFIG_ARM
> +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)

Here may cause other RISC-V platforms build error.
eq, ae350 will compile error as below:
common/board_r.o: in function `initr_caches':
/u-boot-riscv/common/board_r.c:124: undefined reference to `enable_caches'
Makefile:1795: recipe for target 'u-boot' failed

Maybe you can separate this part an isolate patch:
board_r: enable initr_caches for RISC-V ...
And also implement the week function for others.

Thanks,
Rick



>  /*
>   * Some of these functions are needed purely because the functions they
>   * call return void. If we change them to return 0, these stubs can go away.
> @@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = {
>         initr_trace,
>         initr_reloc,
>         /* TODO: could x86/PPC have this also perhaps? */ -#ifdef CONFIG_ARM
> +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
>         initr_caches,
>         /* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
>          *       A temporary mapping of IFC high region is since removed,
> --
> 2.32.0

On Wed, Sep 1, 2021 at 10:06 AM Rick Chen <rickchen36@gmail.com> wrote:
>
> > From: Zong Li <zong.li@sifive.com>
> > Sent: Tuesday, August 31, 2021 5:21 PM
> > To: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>; bmeng.cn@gmail.com; seanga2@gmail.com; green.wan@sifive.com; paul.walmsley@sifive.com; sjg@chromium.org; u-boot@lists.denx.de
> > Cc: Zong Li <zong.li@sifive.com>
> > Subject: [PATCH v4 2/4] riscv: lib: implement enable_caches for sifive cache
> >
> > The enable_caches is a generic hook for architecture-implemented, we define this function to enable composable cache of sifive platforms.
> >
> > In sifive_cache, it invokes the generic cache_enable interface of cache uclass to execute the relative implementation in SiFive ccache driver.
> >
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> >  arch/riscv/Kconfig            |  5 +++++
> >  arch/riscv/lib/Makefile       |  1 +
> >  arch/riscv/lib/sifive_cache.c | 27 +++++++++++++++++++++++++++
> >  common/board_r.c              |  4 ++--
> >  4 files changed, 35 insertions(+), 2 deletions(-)  create mode 100644 arch/riscv/lib/sifive_cache.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4b0c3dffa6..ec651fe0a4 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
> >           The SiFive CLINT block holds memory-mapped control and status registers
> >           associated with software and timer interrupts.
> >
> > +config SIFIVE_CACHE
> > +       bool
> > +       help
> > +         This enables the operations to configure SiFive cache
> > +
> >  config ANDES_PLIC
> >         bool
> >         depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index c4cc41434b..06020fcc2a 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> >  obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
> >  obj-$(CONFIG_CMD_GO) += boot.o
> >  obj-y  += cache.o
> > +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
> >  ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
> >  obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
> >  obj-$(CONFIG_ANDES_PLIC) += andes_plic.o diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c new file mode 100644 index 0000000000..28154878fc
> > --- /dev/null
> > +++ b/arch/riscv/lib/sifive_cache.c
> > @@ -0,0 +1,27 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2021 SiFive, Inc
> > + */
> > +
> > +#include <common.h>
> > +#include <cache.h>
> > +#include <cpu_func.h>
> > +#include <dm.h>
> > +
> > +void enable_caches(void)
> > +{
> > +       struct udevice *dev;
> > +       int ret;
> > +
> > +       /* Enable ways of ccache */
> > +       ret = uclass_get_device_by_driver(UCLASS_CACHE,
> > +                                         DM_DRIVER_GET(sifive_ccache),
> > +                                         &dev);
> > +       if (ret) {
> > +               log_debug("Cannot enable cache ways");
> > +       } else {
> > +               ret = cache_enable(dev);
> > +               if (ret)
> > +                       log_debug("ccache enable failed");
> > +       }
> > +}
> > diff --git a/common/board_r.c b/common/board_r.c index e3e6248a1f..630c2451a2 100644
> > --- a/common/board_r.c
> > +++ b/common/board_r.c
> > @@ -114,7 +114,7 @@ static int initr_reloc(void)
> >         return 0;
> >  }
> >
> > -#ifdef CONFIG_ARM
> > +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
>
> Here may cause other RISC-V platforms build error.
> eq, ae350 will compile error as below:
> common/board_r.o: in function `initr_caches':
> /u-boot-riscv/common/board_r.c:124: undefined reference to `enable_caches'
> Makefile:1795: recipe for target 'u-boot' failed
>
> Maybe you can separate this part an isolate patch:
> board_r: enable initr_caches for RISC-V ...
> And also implement the week function for others.
>

Thanks for reviewing that. I would fix it and send the next version.

> Thanks,
> Rick
>
>
>
> >  /*
> >   * Some of these functions are needed purely because the functions they
> >   * call return void. If we change them to return 0, these stubs can go away.
> > @@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = {
> >         initr_trace,
> >         initr_reloc,
> >         /* TODO: could x86/PPC have this also perhaps? */ -#ifdef CONFIG_ARM
> > +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
> >         initr_caches,
> >         /* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
> >          *       A temporary mapping of IFC high region is since removed,
> > --
> > 2.32.0