| Message ID | 20210721163305.74945-2-xypron.glpk@gmx.de |
|---|---|
| State | Changes Requested |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: enable SBI system reset | expand |
On 7/21/21 12:33 PM, Heinrich Schuchardt wrote: > Add the System Reset Extension and the Hart State Management Extension > definitions. > > Add missing RFENCE Extension enum values. > > The SBI 0.1 extension constants are needed for for the sbi command. Remove > an #ifdef. > > Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc > > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> > --- > v2: > correct constants that were blindly copied from Linux > --- > arch/riscv/include/asm/sbi.h | 36 ++++++++++++++++++++++++++++++++++-- > 1 file changed, 34 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > index 53ca316180..39d5a022e0 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -12,7 +12,6 @@ > #include <linux/types.h> > > enum sbi_ext_id { > -#ifdef CONFIG_SBI_V01 > SBI_EXT_0_1_SET_TIMER = 0x0, > SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, > SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, > @@ -22,11 +21,12 @@ enum sbi_ext_id { > SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, > SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, > SBI_EXT_0_1_SHUTDOWN = 0x8, > -#endif > SBI_EXT_BASE = 0x10, > SBI_EXT_TIME = 0x54494D45, > SBI_EXT_IPI = 0x735049, > SBI_EXT_RFENCE = 0x52464E43, > + SBI_EXT_HSM = 0x48534D, > + SBI_EXT_SRST = 0x53525354, > }; > > enum sbi_ext_base_fid { > @@ -51,6 +51,38 @@ enum sbi_ext_rfence_fid { > SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, > +}; > + > +enum sbi_ext_hsm_fid { > + SBI_EXT_HSM_HART_START = 0, > + SBI_EXT_HSM_HART_STOP, > + SBI_EXT_HSM_HART_STATUS, > +}; > + > +enum sbi_hsm_hart_status { > + SBI_HSM_HART_STATUS_STARTED = 0, > + SBI_HSM_HART_STATUS_STOPPED, > + SBI_HSM_HART_STATUS_START_PENDING, > + SBI_HSM_HART_STATUS_STOP_PENDING, Perhaps add the suspend states from https://github.com/riscv/riscv-sbi-doc/pull/66 > +}; > + > +enum sbi_ext_srst_fid { > + SBI_EXT_SRST_RESET = 0, > +}; > + > +enum sbi_srst_reset_type { > + SBI_SRST_RESET_TYPE_SHUTDOWN = 0, > + SBI_SRST_RESET_TYPE_COLD_REBOOT, > + SBI_SRST_RESET_TYPE_WARM_REBOOT, > +}; > + > +enum sbi_srst_reset_reason { > + SBI_SRST_RESET_REASON_NONE = 0, > + SBI_SRST_RESET_REASON_SYS_FAILURE, > }; > > #ifdef CONFIG_SBI_V01 > -- > 2.30.2 > Reviewed-by: Sean Anderson <seanga2@gmail.com>
On Thu, Jul 22, 2021 at 12:33:03AM +0800, Heinrich Schuchardt wrote: > Add the System Reset Extension and the Hart State Management Extension > definitions. > > Add missing RFENCE Extension enum values. > > The SBI 0.1 extension constants are needed for for the sbi command. Remove > an #ifdef. > > Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc > > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> > --- > v2: > correct constants that were blindly copied from Linux > --- > arch/riscv/include/asm/sbi.h | 36 ++++++++++++++++++++++++++++++++++-- > 1 file changed, 34 insertions(+), 2 deletions(-) Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Hi Heinrich, On Thu, Jul 22, 2021 at 01:02:10AM +0800, Sean Anderson wrote: > On 7/21/21 12:33 PM, Heinrich Schuchardt wrote: > > Add the System Reset Extension and the Hart State Management Extension > > definitions. > > > > Add missing RFENCE Extension enum values. > > > > The SBI 0.1 extension constants are needed for for the sbi command. Remove > > an #ifdef. > > > > Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc > > > > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> > > --- > > v2: > > correct constants that were blindly copied from Linux > > --- > > arch/riscv/include/asm/sbi.h | 36 ++++++++++++++++++++++++++++++++++-- > > 1 file changed, 34 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > > index 53ca316180..39d5a022e0 100644 > > --- a/arch/riscv/include/asm/sbi.h > > +++ b/arch/riscv/include/asm/sbi.h > > @@ -12,7 +12,6 @@ > > #include <linux/types.h> > > > > enum sbi_ext_id { > > -#ifdef CONFIG_SBI_V01 > > SBI_EXT_0_1_SET_TIMER = 0x0, > > SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, > > SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, > > @@ -22,11 +21,12 @@ enum sbi_ext_id { > > SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, > > SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, > > SBI_EXT_0_1_SHUTDOWN = 0x8, > > -#endif > > SBI_EXT_BASE = 0x10, > > SBI_EXT_TIME = 0x54494D45, > > SBI_EXT_IPI = 0x735049, > > SBI_EXT_RFENCE = 0x52464E43, > > + SBI_EXT_HSM = 0x48534D, > > + SBI_EXT_SRST = 0x53525354, > > }; > > > > enum sbi_ext_base_fid { > > @@ -51,6 +51,38 @@ enum sbi_ext_rfence_fid { > > SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, > > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, > > SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, > > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, > > + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, > > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, > > + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, > > +}; > > + > > +enum sbi_ext_hsm_fid { > > + SBI_EXT_HSM_HART_START = 0, > > + SBI_EXT_HSM_HART_STOP, > > + SBI_EXT_HSM_HART_STATUS, > > +}; > > + > > +enum sbi_hsm_hart_status { > > + SBI_HSM_HART_STATUS_STARTED = 0, > > + SBI_HSM_HART_STATUS_STOPPED, > > + SBI_HSM_HART_STATUS_START_PENDING, > > + SBI_HSM_HART_STATUS_STOP_PENDING, > > Perhaps add the suspend states from https://github.com/riscv/riscv-sbi-doc/pull/66 +1 > > > +}; > > + > > +enum sbi_ext_srst_fid { > > + SBI_EXT_SRST_RESET = 0, > > +}; > > + > > +enum sbi_srst_reset_type { > > + SBI_SRST_RESET_TYPE_SHUTDOWN = 0, > > + SBI_SRST_RESET_TYPE_COLD_REBOOT, > > + SBI_SRST_RESET_TYPE_WARM_REBOOT, > > +}; > > + > > +enum sbi_srst_reset_reason { > > + SBI_SRST_RESET_REASON_NONE = 0, > > + SBI_SRST_RESET_REASON_SYS_FAILURE, > > }; > > > > #ifdef CONFIG_SBI_V01 > > -- > > 2.30.2 > > > > Reviewed-by: Sean Anderson <seanga2@gmail.com> Best regards, Leo
Hi Heinrich, I've noticed that there is also a typo in the commit title "risv". Please correct it in v3 patch as well! Thanks! On Thu, Jul 22, 2021 at 12:33:03AM +0800, Heinrich Schuchardt wrote: > Add the System Reset Extension and the Hart State Management Extension > definitions. > > Add missing RFENCE Extension enum values. > > The SBI 0.1 extension constants are needed for for the sbi command. Remove > an #ifdef. > > Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc > > Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> > --- > v2: > correct constants that were blindly copied from Linux > --- > arch/riscv/include/asm/sbi.h | 36 ++++++++++++++++++++++++++++++++++-- > 1 file changed, 34 insertions(+), 2 deletions(-) Best regards, Leo
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 53ca316180..39d5a022e0 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -12,7 +12,6 @@ #include <linux/types.h> enum sbi_ext_id { -#ifdef CONFIG_SBI_V01 SBI_EXT_0_1_SET_TIMER = 0x0, SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, @@ -22,11 +21,12 @@ enum sbi_ext_id { SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, SBI_EXT_0_1_SHUTDOWN = 0x8, -#endif SBI_EXT_BASE = 0x10, SBI_EXT_TIME = 0x54494D45, SBI_EXT_IPI = 0x735049, SBI_EXT_RFENCE = 0x52464E43, + SBI_EXT_HSM = 0x48534D, + SBI_EXT_SRST = 0x53525354, }; enum sbi_ext_base_fid { @@ -51,6 +51,38 @@ enum sbi_ext_rfence_fid { SBI_EXT_RFENCE_REMOTE_FENCE_I = 0, SBI_EXT_RFENCE_REMOTE_SFENCE_VMA, SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID, + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID, + SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA, + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID, + SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA, +}; + +enum sbi_ext_hsm_fid { + SBI_EXT_HSM_HART_START = 0, + SBI_EXT_HSM_HART_STOP, + SBI_EXT_HSM_HART_STATUS, +}; + +enum sbi_hsm_hart_status { + SBI_HSM_HART_STATUS_STARTED = 0, + SBI_HSM_HART_STATUS_STOPPED, + SBI_HSM_HART_STATUS_START_PENDING, + SBI_HSM_HART_STATUS_STOP_PENDING, +}; + +enum sbi_ext_srst_fid { + SBI_EXT_SRST_RESET = 0, +}; + +enum sbi_srst_reset_type { + SBI_SRST_RESET_TYPE_SHUTDOWN = 0, + SBI_SRST_RESET_TYPE_COLD_REBOOT, + SBI_SRST_RESET_TYPE_WARM_REBOOT, +}; + +enum sbi_srst_reset_reason { + SBI_SRST_RESET_REASON_NONE = 0, + SBI_SRST_RESET_REASON_SYS_FAILURE, }; #ifdef CONFIG_SBI_V01
Add the System Reset Extension and the Hart State Management Extension definitions. Add missing RFENCE Extension enum values. The SBI 0.1 extension constants are needed for for the sbi command. Remove an #ifdef. Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> --- v2: correct constants that were blindly copied from Linux --- arch/riscv/include/asm/sbi.h | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) -- 2.30.2