| Message ID | 20210721155849.20994-7-kishon@ti.com |
|---|---|
| State | Accepted |
| Commit | 2b0f7dee5fcd71de11faf2d096d22b241ce920d7 |
| Delegated to: | Lokesh Vutla |
| Headers | show
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Wed, 21 Jul 2021 10:59:11 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 21 Jul 2021 10:59:11 -0500 Received: from a0393678-ssd.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16LFwoVo091982; Wed, 21 Jul 2021 10:59:09 -0500 From: Kishon Vijay Abraham I <kishon@ti.com> To: Lokesh Vutla <lokeshvutla@ti.com>, Simon Glass <sjg@chromium.org>, Tom Rini <trini@konsulko.com> CC: Aswath Govindraju <a-govindraju@ti.com>, Pratyush Yadav <p.yadav@ti.com>, Kishon Vijay Abraham I <kishon@ti.com>, <u-boot@lists.denx.de> Subject: [PATCH v5 06/20] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC Date: Wed, 21 Jul 2021 21:28:35 +0530 Message-ID: <20210721155849.20994-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210721155849.20994-1-kishon@ti.com> References: <20210721155849.20994-1-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <https://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean |
| Series |
TI/Cadence: Add Sierra/Torrent SERDES driver
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expand
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diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index 9047ec6bd3..d417b9268b 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -90,4 +90,9 @@ #define J7200_SERDES0_LANE3_USB 0x2 #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 +/* AM64 */ + +#define AM64_SERDES0_LANE0_PCIE0 0x0 +#define AM64_SERDES0_LANE0_USB 0x1 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */
AM64 has a single lane SERDES which can be configured to be used with either PCIe or USB. Define the possilbe values for the SERDES function in AM64 SoC here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- include/dt-bindings/mux/ti-serdes.h | 5 +++++ 1 file changed, 5 insertions(+)