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[94.134.7.129]) by smtp.gmail.com with ESMTPSA id t9sm16880571wrq.92.2021.07.06.07.22.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jul 2021 07:22:29 -0700 (PDT) From: Daniel Schwierzeck To: u-boot@lists.denx.de Cc: Simon Glass , Stefan Roese , Tom Rini , Daniel Schwierzeck Subject: [PATCH 4/6] MIPS: malta: add DT bindings for PCI host controller Date: Tue, 6 Jul 2021 16:22:20 +0200 Message-Id: <20210706142222.497569-5-daniel.schwierzeck@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210706142222.497569-1-daniel.schwierzeck@gmail.com> References: <20210706142222.497569-1-daniel.schwierzeck@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add DT binding for GT64120 and MSC01 PCI controllers. Only GT64120 is enabled by default to support Qemu. The MSC01 node will be dynamically enabled by Malta board code dependent on the plugged core card. Signed-off-by: Daniel Schwierzeck --- arch/mips/dts/mti,malta.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts index d339229c2a..ef47a340bb 100644 --- a/arch/mips/dts/mti,malta.dts +++ b/arch/mips/dts/mti,malta.dts @@ -29,4 +29,32 @@ u-boot,dm-pre-reloc; }; }; + + pci0@1bd00000 { + compatible = "mips,pci-msc01"; + device_type = "pci"; + reg = <0x1bd00000 0x2000>; + + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x0>; + ranges = <0x01000000 0 0x00000000 0x00000000 0 0x800000 /* I/O */ + 0x02000000 0 0x10000000 0xb0000000 0 0x10000000 /* MEM */>; + + status = "disabled"; + }; + + pci0@1be00000 { + compatible = "marvell,pci-gt64120"; + device_type = "pci"; + reg = <0x1be00000 0x2000>; + + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x0>; + ranges = <0x01000000 0 0x00000000 0x00000000 0 0x20000 /* I/O */ + 0x02000000 0 0x10000000 0x10000000 0 0x8000000 /* MEM */>; + + status = "okay"; + }; };