| Message ID | 20210625132633.14137-1-jbx6244@gmail.com |
|---|---|
| State | Accepted |
| Commit | 571f679d1aa7eb98dcae7691dd34596beda1dfb2 |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | [v2,1/5] rockchip: rk3188-cru-common: sync clock dt-binding header from Linux | expand |
Johan Jonker <jbx6244@gmail.com> 于2021年6月25日周五 下午9:30写道： > > In order to update the DT for rk3066 and rk3188 > sync the clock dt-binding header. > This is the state as of v5.12 in Linux. > > Signed-off-by: Johan Jonker <jbx6244@gmail.com> > Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > include/dt-bindings/clock/rk3188-cru-common.h | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h > index 1e7931da0c..afad90680f 100644 > --- a/include/dt-bindings/clock/rk3188-cru-common.h > +++ b/include/dt-bindings/clock/rk3188-cru-common.h > @@ -1,4 +1,4 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > +/* SPDX-License-Identifier: GPL-2.0-or-later */ > /* > * Copyright (c) 2014 MundoReader S.L. > * Author: Heiko Stuebner <heiko@sntech.de> > @@ -59,12 +59,14 @@ > #define ACLK_LCDC1 196 > #define ACLK_GPU 197 > #define ACLK_SMC 198 > -#define ACLK_CIF 199 > +#define ACLK_CIF1 199 > #define ACLK_IPP 200 > #define ACLK_RGA 201 > #define ACLK_CIF0 202 > #define ACLK_CPU 203 > #define ACLK_PERI 204 > +#define ACLK_VEPU 205 > +#define ACLK_VDPU 206 > > /* pclk gates */ > #define PCLK_GRF 320 > @@ -125,8 +127,12 @@ > #define HCLK_NANDC0 467 > #define HCLK_CPU 468 > #define HCLK_PERI 469 > +#define HCLK_CIF1 470 > +#define HCLK_VEPU 471 > +#define HCLK_VDPU 472 > +#define HCLK_HDMI 473 > > -#define CLK_NR_CLKS (HCLK_PERI + 1) > +#define CLK_NR_CLKS (HCLK_HDMI + 1) > > /* soft-reset indices */ > #define SRST_MCORE 2 > -- > 2.11.0 >
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 1e7931da0c..afad90680f 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> @@ -59,12 +59,14 @@ #define ACLK_LCDC1 196 #define ACLK_GPU 197 #define ACLK_SMC 198 -#define ACLK_CIF 199 +#define ACLK_CIF1 199 #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 #define ACLK_CPU 203 #define ACLK_PERI 204 +#define ACLK_VEPU 205 +#define ACLK_VDPU 206 /* pclk gates */ #define PCLK_GRF 320 @@ -125,8 +127,12 @@ #define HCLK_NANDC0 467 #define HCLK_CPU 468 #define HCLK_PERI 469 +#define HCLK_CIF1 470 +#define HCLK_VEPU 471 +#define HCLK_VDPU 472 +#define HCLK_HDMI 473 -#define CLK_NR_CLKS (HCLK_PERI + 1) +#define CLK_NR_CLKS (HCLK_HDMI + 1) /* soft-reset indices */ #define SRST_MCORE 2