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Wed, 23 Jun 2021 23:34:46 -0700 Envelope-to: git@xilinx.com, rfried.dev@gmail.com, somaashokreddy@gmail.com, u-boot@lists.denx.de, monstr@monstr.eu, joe.hershberger@ni.com Received: from [10.140.6.65] (port=50954 helo=xhdashokred41.localdomain) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lwIwm-0001PN-Lj; Wed, 23 Jun 2021 23:34:45 -0700 Received: by xhdashokred41.localdomain (Postfix, from userid 2896) id DF48910027D; Thu, 24 Jun 2021 00:34:43 -0600 (MDT) From: Ashok Reddy Soma To: CC: , , , , , Ashok Reddy Soma Subject: [PATCH 1/2] net: xilinx: axi_emac: Cleanup of of_to_plat() Date: Thu, 24 Jun 2021 00:34:40 -0600 Message-ID: <20210624063441.24072-2-ashok.reddy.soma@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210624063441.24072-1-ashok.reddy.soma@xilinx.com> References: <20210624063441.24072-1-ashok.reddy.soma@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4cd5826b-c52f-41a5-5414-08d936da300d X-MS-TrafficTypeDiagnostic: BN7PR02MB4243: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:142; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2021 06:34:58.5666 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cd5826b-c52f-41a5-5414-08d936da300d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT064.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR02MB4243 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean There are lot of accesses to priv data in of_to_plat(), which is incorrect. Create a platform data structure and use it in of_to_plat(), then copy all platform data to priv data in probe. Signed-off-by: Ashok Reddy Soma Reviewed-by: Ramon Fried --- drivers/net/xilinx_axi_emac.c | 47 ++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 2ce6271afe..cfc6082475 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -87,6 +87,16 @@ struct axidma_reg { u32 tail_hi; /* TAILDESC high 32 bit */ }; +/* Platform data structures */ +struct axidma_plat { + struct eth_pdata eth_pdata; + struct axidma_reg *dmatx; + struct axidma_reg *dmarx; + int phyaddr; + u8 eth_hasnobuf; + int phy_of_handle; +}; + /* Private driver structures */ struct axidma_priv { struct axidma_reg *dmatx; @@ -690,9 +700,20 @@ static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad, static int axi_emac_probe(struct udevice *dev) { + struct axidma_plat *plat = dev_get_plat(dev); + struct eth_pdata *pdata = &plat->eth_pdata; struct axidma_priv *priv = dev_get_priv(dev); int ret; + priv->iobase = (struct axi_regs *)pdata->iobase; + priv->dmatx = plat->dmatx; + /* RX channel offset is 0x30 */ + priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30); + priv->eth_hasnobuf = plat->eth_hasnobuf; + priv->phyaddr = plat->phyaddr; + priv->phy_of_handle = plat->phy_of_handle; + priv->interface = pdata->phy_interface; + priv->bus = mdio_alloc(); priv->bus->read = axiemac_miiphy_read; priv->bus->write = axiemac_miiphy_write; @@ -729,14 +750,13 @@ static const struct eth_ops axi_emac_ops = { static int axi_emac_of_to_plat(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_plat(dev); - struct axidma_priv *priv = dev_get_priv(dev); + struct axidma_plat *plat = dev_get_plat(dev); + struct eth_pdata *pdata = &plat->eth_pdata; int node = dev_of_offset(dev); int offset = 0; const char *phy_mode; pdata->iobase = dev_read_addr(dev); - priv->iobase = (struct axi_regs *)pdata->iobase; offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "axistream-connected"); @@ -744,21 +764,19 @@ static int axi_emac_of_to_plat(struct udevice *dev) printf("%s: axistream is not found\n", __func__); return -EINVAL; } - priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob, + plat->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob, offset, "reg"); - if (!priv->dmatx) { + if (!plat->dmatx) { printf("%s: axi_dma register space not found\n", __func__); return -EINVAL; } - /* RX channel offset is 0x30 */ - priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30); - priv->phyaddr = -1; + plat->phyaddr = -1; offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); if (offset > 0) { - priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); - priv->phy_of_handle = offset; + plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); + plat->phy_of_handle = offset; } phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); @@ -768,13 +786,12 @@ static int axi_emac_of_to_plat(struct udevice *dev) printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } - priv->interface = pdata->phy_interface; - priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, + plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, "xlnx,eth-hasnobuf"); - printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, - priv->phyaddr, phy_string_for_interface(priv->interface)); + printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase, + plat->phyaddr, phy_string_for_interface(pdata->phy_interface)); return 0; } @@ -793,5 +810,5 @@ U_BOOT_DRIVER(axi_emac) = { .remove = axi_emac_remove, .ops = &axi_emac_ops, .priv_auto = sizeof(struct axidma_priv), - .plat_auto = sizeof(struct eth_pdata), + .plat_auto = sizeof(struct axidma_plat), };