From patchwork Tue Jun 22 06:34:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1495463 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=LdAmiI6u; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G8Gq24Jw0z9sXk for ; Tue, 22 Jun 2021 16:35:10 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CDF6B829A6; Tue, 22 Jun 2021 08:34:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="LdAmiI6u"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6CDE6829BF; Tue, 22 Jun 2021 08:34:47 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7B17E8020E for ; Tue, 22 Jun 2021 08:34:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=lokeshvutla@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 15M6YdIA005974 for ; Tue, 22 Jun 2021 01:34:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1624343679; bh=NhD5A86MKRh9Bq7S9iTcevPCtA63/Zz69gzmxU4BcUM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LdAmiI6uTmkFoojpsYcfK6OyUFOJuwpz0Rmc1j5kBItsHHmebt8DLXN2D/wbp60jv WxBeP6G0CWUPuE0sQWXRt/SK/Upcfi3NFAampE+e8vnX0j1cq23mr2TMVauyr01FU7 ZsCiDlyh4H91JUTbOftGVtEnEDoigUeobkRCkS98= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 15M6Ydgg056796 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Tue, 22 Jun 2021 01:34:39 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 22 Jun 2021 01:34:38 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 22 Jun 2021 01:34:38 -0500 Received: from lokesh-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 15M6YVGB066559; Tue, 22 Jun 2021 01:34:36 -0500 From: Lokesh Vutla To: CC: Lokesh Vutla , Keerthy , Suman Anna Subject: [PATCH v2 2/5] remoteproc: pru: Add support for various PRU cores on K3 AM65x SoCs Date: Tue, 22 Jun 2021 12:04:28 +0530 Message-ID: <20210622063431.3151-3-lokeshvutla@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210622063431.3151-1-lokeshvutla@ti.com> References: <20210622063431.3151-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Keerthy The K3 AM65x family of SoCs have the next generation of the PRU-ICSS processor subsystem, commonly referred to as ICSSG. Each ICSSG processor subsystem on AM65x SR1.0 contains two primary PRU cores and two new auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised ICSSG IP that is based off the subsequent IP revision used on J721E SoCs. This IP instance has two new custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs. Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than a PRU), Control and debug feature sets, but is different in terms of sub-modules integrated around it and does not have the full capabilities associated with a PRU core. The RTU core is typically used to aid a PRU core in accelerating data transfers, while the Tx_PRU cores is normally used to control the TX L2 FIFO if enabled in Ethernet applications. Both can also be used to run independent applications. The RTU and Tx_PRU cores though share the same Data RAMs as the PRU cores, so the memories have to be partitioned carefully between different applications. The new cores also support a new sub-module called Task Manager to support two different context thread executions. The driver currently supports the AM65xx SoC Signed-off-by: Keerthy Signed-off-by: Suman Anna Signed-off-by: Murali Karicheri Signed-off-by: Roger Quadros Signed-off-by: Lokesh Vutla --- MAINTAINERS | 1 + drivers/remoteproc/Kconfig | 11 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/pru_rproc.c | 461 +++++++++++++++++++++++++++++++++ 4 files changed, 474 insertions(+) create mode 100644 drivers/remoteproc/pru_rproc.c diff --git a/MAINTAINERS b/MAINTAINERS index b85a968ac3..bc809acd01 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -513,6 +513,7 @@ F: drivers/phy/phy-ti-am654.c F: drivers/phy/ti-pipe3-phy.c F: drivers/ram/k3* F: drivers/remoteproc/k3_system_controller.c +F: drivers/remoteproc/pruc_rpoc.c F: drivers/remoteproc/ti* F: drivers/reset/reset-ti-sci.c F: drivers/rtc/davinci.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 7c2e4804b5..24e536463b 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -81,4 +81,15 @@ config REMOTEPROC_TI_POWER help Say 'y' here to add support for TI power processors such as those found on certain TI keystone and OMAP generation SoCs. + +config REMOTEPROC_TI_PRU + bool "Support for TI's K3 based PRU remoteproc driver" + select REMOTEPROC + depends on DM + depends on TI_PRUSS + depends on ARCH_K3 + depends on OF_CONTROL + help + Say 'y' here to add support for TI' K3 remoteproc driver. + endmenu diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 69ae7bd1e8..f0e83451d6 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o +obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c new file mode 100644 index 0000000000..924070a76b --- /dev/null +++ b/drivers/remoteproc/pru_rproc.c @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PRU-RTU remoteproc driver for various SoCs + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Keerthy + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PRU_ICSS_PRU_CTRL registers */ +#define PRU_CTRL_CTRL 0x0000 +#define PRU_CTRL_STS 0x0004 +#define PRU_CTRL_WAKEUP_EN 0x0008 +#define PRU_CTRL_CYCLE 0x000C +#define PRU_CTRL_STALL 0x0010 +#define PRU_CTRL_CTBIR0 0x0020 +#define PRU_CTRL_CTBIR1 0x0024 +#define PRU_CTRL_CTPPR0 0x0028 +#define PRU_CTRL_CTPPR1 0x002C + +/* CTRL register bit-fields */ +#define CTRL_CTRL_SOFT_RST_N BIT(0) +#define CTRL_CTRL_EN BIT(1) +#define CTRL_CTRL_SLEEPING BIT(2) +#define CTRL_CTRL_CTR_EN BIT(3) +#define CTRL_CTRL_SINGLE_STEP BIT(8) +#define CTRL_CTRL_RUNSTATE BIT(15) + +#define RPROC_FLAGS_SHIFT 16 +#define RPROC_FLAGS_NONE 0 +#define RPROC_FLAGS_ELF_PHDR BIT(0 + RPROC_FLAGS_SHIFT) +#define RPROC_FLAGS_ELF_SHDR BIT(1 + RPROC_FLAGS_SHIFT) + +/** + * enum pru_mem - PRU core memory range identifiers + */ +enum pru_mem { + PRU_MEM_IRAM = 0, + PRU_MEM_CTRL, + PRU_MEM_DEBUG, + PRU_MEM_MAX, +}; + +struct pru_privdata { + phys_addr_t pru_iram; + phys_addr_t pru_ctrl; + phys_addr_t pru_debug; + fdt_size_t pru_iramsz; + fdt_size_t pru_ctrlsz; + fdt_size_t pru_debugsz; + const char *fw_name; + u32 iram_da; + u32 pdram_da; + u32 sdram_da; + u32 shrdram_da; + u32 bootaddr; + int id; + struct pruss *prusspriv; +}; + +static inline u32 pru_control_read_reg(struct pru_privdata *pru, unsigned int reg) +{ + return readl(pru->pru_ctrl + reg); +} + +static inline +void pru_control_write_reg(struct pru_privdata *pru, unsigned int reg, u32 val) +{ + writel(val, pru->pru_ctrl + reg); +} + +static inline +void pru_control_set_reg(struct pru_privdata *pru, unsigned int reg, + u32 mask, u32 set) +{ + u32 val; + + val = pru_control_read_reg(pru, reg); + val &= ~mask; + val |= (set & mask); + pru_control_write_reg(pru, reg, val); +} + +/** + * pru_rproc_set_ctable() - set the constant table index for the PRU + * @rproc: the rproc instance of the PRU + * @c: constant table index to set + * @addr: physical address to set it to + */ +static int pru_rproc_set_ctable(struct pru_privdata *pru, enum pru_ctable_idx c, u32 addr) +{ + unsigned int reg; + u32 mask, set; + u16 idx; + u16 idx_mask; + + /* pointer is 16 bit and index is 8-bit so mask out the rest */ + idx_mask = (c >= PRU_C28) ? 0xFFFF : 0xFF; + + /* ctable uses bit 8 and upwards only */ + idx = (addr >> 8) & idx_mask; + + /* configurable ctable (i.e. C24) starts at PRU_CTRL_CTBIR0 */ + reg = PRU_CTRL_CTBIR0 + 4 * (c >> 1); + mask = idx_mask << (16 * (c & 1)); + set = idx << (16 * (c & 1)); + + pru_control_set_reg(pru, reg, mask, set); + + return 0; +} + +/** + * pru_start() - start the pru processor + * @dev: corresponding k3 remote processor device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int pru_start(struct udevice *dev) +{ + struct pru_privdata *priv; + int val = 0; + + priv = dev_get_priv(dev); + + pru_rproc_set_ctable(priv, PRU_C28, 0x100 << 8); + + val = CTRL_CTRL_EN | ((priv->bootaddr >> 2) << 16); + writel(val, priv->pru_ctrl + PRU_CTRL_CTRL); + + return 0; +} + +/** + * pru_stop() - Stop pru processor + * @dev: corresponding k3 remote processor device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int pru_stop(struct udevice *dev) +{ + struct pru_privdata *priv; + int val = 0; + + priv = dev_get_priv(dev); + + val = readl(priv->pru_ctrl + PRU_CTRL_CTRL); + val &= ~CTRL_CTRL_EN; + writel(val, priv->pru_ctrl + PRU_CTRL_CTRL); + + return 0; +} + +/** + * pru_init() - Initialize the remote processor + * @dev: rproc device pointer + * + * Return: 0 if all went ok, else return appropriate error + */ +static int pru_init(struct udevice *dev) +{ + return 0; +} + +/* + * Convert PRU device address (data spaces only) to kernel virtual address + * + * Each PRU has access to all data memories within the PRUSS, accessible at + * different ranges. So, look through both its primary and secondary Data + * RAMs as well as any shared Data RAM to convert a PRU device address to + * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data + * RAM1 is primary Data RAM for PRU1. + */ +static void *pru_d_da_to_pa(struct pru_privdata *priv, u32 da, int len) +{ + u32 offset; + void *pa = NULL; + phys_addr_t dram0, dram1, shrdram2; + u32 dram0sz, dram1sz, shrdram2sz; + + if (len <= 0) + return NULL; + + dram0 = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM0].pa; + dram1 = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].pa; + shrdram2 = priv->prusspriv->mem_regions[PRUSS_MEM_SHRD_RAM2].pa; + dram0sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM0].size; + dram1sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].size; + shrdram2sz = priv->prusspriv->mem_regions[PRUSS_MEM_SHRD_RAM2].size; + + /* PRU1 has its local RAM addresses reversed */ + if (priv->id == 1) { + dram1 = dram0; + dram1sz = dram0sz; + + dram0 = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].pa; + dram0sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].size; + } + + if (da >= priv->pdram_da && da + len <= priv->pdram_da + dram0sz) { + offset = da - priv->pdram_da; + pa = (__force void *)(dram0 + offset); + } else if (da >= priv->sdram_da && + da + len <= priv->sdram_da + dram1sz) { + offset = da - priv->sdram_da; + pa = (__force void *)(dram1 + offset); + } else if (da >= priv->shrdram_da && + da + len <= priv->shrdram_da + shrdram2sz) { + offset = da - priv->shrdram_da; + pa = (__force void *)(shrdram2 + offset); + } + + return pa; +} + +/* + * Convert PRU device address (instruction space) to kernel virtual address + * + * A PRU does not have an unified address space. Each PRU has its very own + * private Instruction RAM, and its device address is identical to that of + * its primary Data RAM device address. + */ +static void *pru_i_da_to_pa(struct pru_privdata *priv, u32 da, int len) +{ + u32 offset; + void *pa = NULL; + + if (len <= 0) + return NULL; + + if (da >= priv->iram_da && + da + len <= priv->iram_da + priv->pru_iramsz) { + offset = da - priv->iram_da; + pa = (__force void *)(priv->pru_iram + offset); + } + + return pa; +} + +/* PRU-specific address translator */ +static void *pru_da_to_pa(struct pru_privdata *priv, u64 da, int len, u32 flags) +{ + void *pa; + u32 exec_flag; + + exec_flag = ((flags & RPROC_FLAGS_ELF_SHDR) ? flags & SHF_EXECINSTR : + ((flags & RPROC_FLAGS_ELF_PHDR) ? flags & PF_X : 0)); + + if (exec_flag) + pa = pru_i_da_to_pa(priv, da, len); + else + pa = pru_d_da_to_pa(priv, da, len); + + return pa; +} + +/* + * Custom memory copy implementation for ICSSG PRU/RTU Cores + * + * The ICSSG PRU/RTU cores have a memory copying issue with IRAM memories, that + * is not seen on previous generation SoCs. The data is reflected properly in + * the IRAM memories only for integer (4-byte) copies. Any unaligned copies + * result in all the other pre-existing bytes zeroed out within that 4-byte + * boundary, thereby resulting in wrong text/code in the IRAMs. Also, the + * IRAM memory port interface does not allow any 8-byte copies (as commonly + * used by ARM64 memcpy implementation) and throws an exception. The DRAM + * memory ports do not show this behavior. Use this custom copying function + * to properly load the PRU/RTU firmware images on all memories for simplicity. + * + * TODO: Improve the function to deal with additional corner cases like + * unaligned copy sizes or sub-integer trailing bytes when the need arises. + */ +static int pru_rproc_memcpy(void *dest, void *src, size_t count) +{ + const int *s = src; + int *d = dest; + int size = count / 4; + int *tmp_src = NULL; + + /* limited to 4-byte aligned addresses and copy sizes */ + if ((long)dest % 4 || count % 4) + return -EINVAL; + + /* src offsets in ELF firmware image can be non-aligned */ + if ((long)src % 4) { + tmp_src = malloc(count); + if (!tmp_src) + return -ENOMEM; + + memcpy(tmp_src, src, count); + s = tmp_src; + } + + while (size--) + *d++ = *s++; + + kfree(tmp_src); + + return 0; +} + +/** + * pru_load() - Load pru firmware + * @dev: corresponding k3 remote processor device + * @addr: Address on the RAM from which firmware is to be loaded + * @size: Size of the pru firmware in bytes + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int pru_load(struct udevice *dev, ulong addr, ulong size) +{ + struct pru_privdata *priv; + Elf32_Ehdr *ehdr; + Elf32_Phdr *phdr; + int i, ret = 0; + + priv = dev_get_priv(dev); + + ehdr = (Elf32_Ehdr *)addr; + phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); + + /* go through the available ELF segments */ + for (i = 0; i < ehdr->e_phnum; i++, phdr++) { + u32 da = phdr->p_paddr; + u32 memsz = phdr->p_memsz; + u32 filesz = phdr->p_filesz; + u32 offset = phdr->p_offset; + void *ptr; + + if (phdr->p_type != PT_LOAD) + continue; + + dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n", + phdr->p_type, da, memsz, filesz); + + if (filesz > memsz) { + dev_dbg(dev, "bad phdr filesz 0x%x memsz 0x%x\n", + filesz, memsz); + ret = -EINVAL; + break; + } + + if (offset + filesz > size) { + dev_dbg(dev, "truncated fw: need 0x%x avail 0x%zx\n", + offset + filesz, size); + ret = -EINVAL; + break; + } + + /* grab the kernel address for this device address */ + ptr = pru_da_to_pa(priv, da, memsz, + RPROC_FLAGS_ELF_PHDR | phdr->p_flags); + if (!ptr) { + dev_dbg(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz); + ret = -EINVAL; + break; + } + + /* skip the memzero logic performed by remoteproc ELF loader */ + if (!phdr->p_filesz) + continue; + + ret = pru_rproc_memcpy(ptr, + (void *)addr + phdr->p_offset, filesz); + if (ret) { + dev_dbg(dev, "PRU custom memory copy failed for da 0x%x memsz 0x%x\n", + da, memsz); + break; + } + } + + priv->bootaddr = ehdr->e_entry; + + return ret; +} + +static const struct dm_rproc_ops pru_ops = { + .init = pru_init, + .start = pru_start, + .stop = pru_stop, + .load = pru_load, +}; + +static void pru_set_id(struct pru_privdata *priv, struct udevice *dev) +{ + u32 mask2 = 0x38000; + + if (device_is_compatible(dev, "ti,am654-rtu")) + mask2 = 0x6000; + + if (device_is_compatible(dev, "ti,am654-tx-pru")) + mask2 = 0xc000; + + if ((priv->pru_iram & mask2) == mask2) + priv->id = 1; + else + priv->id = 0; +} + +/** + * pru_probe() - Basic probe + * @dev: corresponding k3 remote processor device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int pru_probe(struct udevice *dev) +{ + struct pru_privdata *priv; + ofnode node; + + node = dev_ofnode(dev); + + priv = dev_get_priv(dev); + priv->prusspriv = dev_get_priv(dev->parent); + + priv->pru_iram = devfdt_get_addr_size_index(dev, PRU_MEM_IRAM, + &priv->pru_iramsz); + priv->pru_ctrl = devfdt_get_addr_size_index(dev, PRU_MEM_CTRL, + &priv->pru_ctrlsz); + priv->pru_debug = devfdt_get_addr_size_index(dev, PRU_MEM_DEBUG, + &priv->pru_debugsz); + + priv->iram_da = 0; + priv->pdram_da = 0; + priv->sdram_da = 0x2000; + priv->shrdram_da = 0x10000; + + pru_set_id(priv, dev); + + return 0; +} + +static const struct udevice_id pru_ids[] = { + { .compatible = "ti,am654-pru"}, + { .compatible = "ti,am654-rtu"}, + { .compatible = "ti,am654-tx-pru" }, + {} +}; + +U_BOOT_DRIVER(pru) = { + .name = "pru", + .of_match = pru_ids, + .id = UCLASS_REMOTEPROC, + .ops = &pru_ops, + .probe = pru_probe, + .priv_auto = sizeof(struct pru_privdata), +};