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[v2] riscv: andes_plic: Fix riscv_get_ipi() mask

Message ID 20210615054557.376750-1-bmeng.cn@gmail.com
State Accepted
Commit 62ce0a02f9e5bda51a05c5f735e5a75f6c4bbb54
Delegated to: Andes
Headers show
Series [v2] riscv: andes_plic: Fix riscv_get_ipi() mask | expand

Commit Message

Bin Meng June 15, 2021, 5:45 a.m. UTC
Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().

Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>


Changes in v2:
- remove RFT tag
- update commit message with "Fixes" tag along with the commit id

 arch/riscv/lib/andes_plic.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 221a5fe324..5e113ee8c9 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -105,9 +105,11 @@  int riscv_clear_ipi(int hart)
 int riscv_get_ipi(int hart, int *pending)
+	unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
 	*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
-	*pending = !!(*pending & SEND_IPI_TO_HART(hart));
+	*pending = !!(*pending & ipi);
 	return 0;