From patchwork Sun Jun 13 08:48:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siew Chin Lim X-Patchwork-Id: 1491370 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G2pDz5plFz9sWk for ; Sun, 13 Jun 2021 18:50:11 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2B11D82849; Sun, 13 Jun 2021 10:49:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7FDDB81671; Sun, 13 Jun 2021 10:49:22 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 52D5E80C72 for ; Sun, 13 Jun 2021 10:49:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=elly.siew.chin.lim@intel.com IronPort-SDR: 2BuT0FnCn7jXEdW3oDPdDkiQ9K8heiFnIXbyLE6Xx8bB6t7OuF1ekUAFX2o6DKdXpMShmwyAMn 217oVfEJ1kJA== X-IronPort-AV: E=McAfee;i="6200,9189,10013"; a="185398435" X-IronPort-AV: E=Sophos;i="5.83,270,1616482800"; d="scan'208";a="185398435" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2021 01:49:13 -0700 IronPort-SDR: QvUTlRB4fFl/Rx25DqDkpI1P+pkzj6+3WW6d7HvZIpnG/PMpw99GS4O4uCFr8UTUMHXO6iWPVg wOo4m5tHkelQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,270,1616482800"; d="scan'208";a="441941640" Received: from pg-iccf0307.altera.com ([10.104.1.103]) by orsmga007.jf.intel.com with ESMTP; 13 Jun 2021 01:49:11 -0700 From: Siew Chin Lim To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Simon Goldschmidt , Tien Fong Chee , Dalon Westergreen , Simon Glass , Yau Wai Gan , Siew Chin Lim Subject: [v3 06/17] arm: socfpga: Get clock manager base address for Intel N5X device Date: Sun, 13 Jun 2021 16:48:41 +0800 Message-Id: <20210613084852.30868-7-elly.siew.chin.lim@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20210613084852.30868-1-elly.siew.chin.lim@intel.com> References: <20210613084852.30868-1-elly.siew.chin.lim@intel.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add N5X clock manager to socfpga_get_managers_addr function. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/misc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 64a7c9d652..9305bec38a 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -254,6 +254,9 @@ void socfpga_get_managers_addr(void) #ifdef CONFIG_TARGET_SOCFPGA_AGILEX ret = socfpga_get_base_addr("intel,agilex-clkmgr", &socfpga_clkmgr_base); +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) + ret = socfpga_get_base_addr("intel,n5x-clkmgr", + &socfpga_clkmgr_base); #else ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); #endif