From patchwork Sun Jun 13 08:48:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siew Chin Lim X-Patchwork-Id: 1491381 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G2pHV6F42z9sWk for ; Sun, 13 Jun 2021 18:52:22 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D7D878293E; Sun, 13 Jun 2021 10:50:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 3C18F82935; Sun, 13 Jun 2021 10:50:24 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6AB13814A4 for ; Sun, 13 Jun 2021 10:49:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=elly.siew.chin.lim@intel.com IronPort-SDR: 9H9FmgA5dQqlgi/027jkhR9djzRz/g1G02TUygCm2QVOWIiHZ/AjLLVMxcxZKcXF7YJ2hoix6N 5WJ+IdK7SZSw== X-IronPort-AV: E=McAfee;i="6200,9189,10013"; a="185398470" X-IronPort-AV: E=Sophos;i="5.83,270,1616482800"; d="scan'208";a="185398470" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2021 01:49:37 -0700 IronPort-SDR: WoeU7pGjJVREGW67FZMO1dlx80UREWfETDpxyvw/qKdeF5zYaxW59KUl5CYVD7AzYrmIIBdmtn 82xsdEYfW0tQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,270,1616482800"; d="scan'208";a="441941695" Received: from pg-iccf0307.altera.com ([10.104.1.103]) by orsmga007.jf.intel.com with ESMTP; 13 Jun 2021 01:49:35 -0700 From: Siew Chin Lim To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Simon Goldschmidt , Tien Fong Chee , Dalon Westergreen , Simon Glass , Yau Wai Gan , Siew Chin Lim Subject: [v3 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X device Date: Sun, 13 Jun 2021 16:48:50 +0800 Message-Id: <20210613084852.30868-16-elly.siew.chin.lim@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20210613084852.30868-1-elly.siew.chin.lim@intel.com> References: <20210613084852.30868-1-elly.siew.chin.lim@intel.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Add device tree for N5X. Signed-off-by: Siew Chin Lim Signed-off-by: Tien Fong Chee --- v3: - Update comment for memory example code - Move all common dts settings for N5X from socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi - Remove unused parameter "u-boot,boot0" v2: - Remove socfpga_n5x.dtsi - Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update n5x data accordingly. --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_n5x-u-boot.dtsi | 175 ++++++++++++++++++ arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 67 +++++++ ...agilex_socdk.dts => socfpga_n5x_socdk.dts} | 25 ++- 4 files changed, 262 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} (81%) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 096068261d..8a513e2a87 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -393,6 +393,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb \ + socfpga_n5x_socdk.dtb \ socfpga_stratix10_socdk.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi new file mode 100644 index 0000000000..d144116e71 --- /dev/null +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2020-2021 Intel Corporation + */ + +#include "socfpga_soc64_fit-u-boot.dtsi" + +/{ + memory { + #address-cells = <2>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + }; + + soc { + u-boot,dm-pre-reloc; + + ccu: cache-controller@f7000000 { + compatible = "arteris,ncore-ccu"; + reg = <0xf7000000 0x100900>; + u-boot,dm-pre-reloc; + }; + }; +}; + +&clkmgr { + compatible = "intel,n5x-clkmgr"; + u-boot,dm-pre-reloc; +}; + + +&gmac1 { + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + clocks = <&clkmgr N5X_EMAC1_CLK>; +}; + +&gmac2 { + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + clocks = <&clkmgr N5X_EMAC2_CLK>; +}; + +&i2c0 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + reset-names = "i2c"; +}; + +&i2c1 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + reset-names = "i2c"; +}; + +&i2c2 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + reset-names = "i2c"; +}; + +&i2c3 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + reset-names = "i2c"; +}; + +&i2c4 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + reset-names = "i2c"; +}; + +&memclkmgr { + u-boot,dm-pre-reloc; +}; + + +&mmc { + clocks = <&clkmgr N5X_L4_MP_CLK>, + <&clkmgr N5X_SDMMC_CLK>; + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; +}; + +&pdma { + clocks = <&clkmgr N5X_L4_MAIN_CLK>; +}; + +&spi0 { + clocks = <&clkmgr N5X_L4_MAIN_CLK>; +}; + +&spi1 { + clocks = <&clkmgr N5X_L4_MAIN_CLK>; +}; + +&timer0 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&timer1 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&timer2 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&timer3 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&rst { + compatible = "altr,rst-mgr"; + altr,modrst-offset = <0x20>; + u-boot,dm-pre-reloc; +}; + +&sdr { + compatible = "intel,sdr-ctl-n5x"; + resets = <&rst DDRSCH_RESET>; + clocks = <&memclkmgr>; + clock-names = "mem_clk"; + u-boot,dm-pre-reloc; +}; + +&sysmgr { + compatible = "altr,sys-mgr", "syscon"; + u-boot,dm-pre-reloc; +}; + +&uart0 { + clocks = <&clkmgr N5X_L4_SP_CLK>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clocks = <&clkmgr N5X_L4_SP_CLK>; +}; + +&usb0 { + clocks = <&clkmgr N5X_USB_CLK>; + disable-over-current; + u-boot,dm-pre-reloc; +}; + +&usb1 { + clocks = <&clkmgr N5X_USB_CLK>; + u-boot,dm-pre-reloc; +}; + +&watchdog0 { + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; + u-boot,dm-pre-reloc; +}; + +&watchdog1 { + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; +}; + +&watchdog2 { + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; +}; + +&watchdog3 { + clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>; +}; + diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi new file mode 100644 index 0000000000..612d394019 --- /dev/null +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2020-2021 Intel Corporation + */ + +#include "socfpga_n5x-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + i2c0 = &i2c1; + }; + + memory { + /* + * Memory type: DDR4 (interleaving mode) + * 16GB + * <0 0x00000000 0 0x80000000>, + * <4 0x80000000 3 0x80000000>; + * + * 8GB + * <0 0x00000000 0 0x80000000>, + * <2 0x80000000 1 0x80000000>; + * + * 4GB + * <0 0x00000000 0 0x80000000>, + * <1 0x80000000 0 0x80000000>; + * + * Memory type: LPDDR4 (non-interleaving mode) + * Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for secure + * region. + */ + reg = <0 0x00000000 0 0x60000000>, + <0x10 0x00100000 0 0x40000000>; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + u-boot,dm-pre-reloc; +}; + +&i2c1 { + status = "okay"; +}; + +&nand { + u-boot,dm-pre-reloc; +}; + +&mmc { + drvsel = <3>; + smplsel = <0>; + u-boot,dm-pre-reloc; +}; + +&qspi { + status = "okay"; +}; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_n5x_socdk.dts similarity index 81% copy from arch/arm/dts/socfpga_agilex_socdk.dts copy to arch/arm/dts/socfpga_n5x_socdk.dts index bcdeecc0e0..4cb71b5de3 100644 --- a/arch/arm/dts/socfpga_agilex_socdk.dts +++ b/arch/arm/dts/socfpga_n5x_socdk.dts @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2020-2021, Intel Corporation */ #include "socfpga_agilex.dtsi" +#include / { - model = "SoCFPGA Agilex SoCDK"; + model = "eASIC N5X SoCDK"; aliases { serial0 = &uart0; @@ -47,6 +48,18 @@ osc1 { clock-frequency = <25000000>; }; + + dram_eosc_clk: dram-eosc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + }; + + memclkmgr: mem-clock-controller@f8040000 { + compatible = "intel,n5x-mem-clkmgr"; + reg = <0xf8040000 0x1000>; + #clock-cells = <0>; + clocks = <&dram_eosc_clk>, <&f2s_free_clk>; }; }; }; @@ -59,8 +72,8 @@ status = "okay"; phy-mode = "rgmii"; phy-handle = <&phy0>; - max-frame-size = <9000>; + clocks = <&clkmgr N5X_EMAC0_CLK>; mdio0 { #address-cells = <1>; @@ -98,14 +111,14 @@ &usb0 { status = "okay"; - disable-over-current; }; -&watchdog0 { +&usb1 { status = "okay"; }; &qspi { + status = "okay"; flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -116,7 +129,7 @@ m25p,fast-read; cdns,page-size = <256>; cdns,block-size = <16>; - cdns,read-delay = <1>; + cdns,read-delay = <3>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>;