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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id o21sm1686080ejg.49.2021.06.03.22.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 22:51:07 -0700 (PDT) From: Bin Meng To: Rick Chen , Leo , U-Boot Mailing List Subject: [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes Date: Fri, 4 Jun 2021 13:51:11 +0800 Message-Id: <20210604055113.3630286-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604055113.3630286-1-bmeng.cn@gmail.com> References: <20210604055113.3630286-1-bmeng.cn@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean PLIC nodes don't have child nodes, so #address-cells is not needed. Signed-off-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/ae350_32.dts | 2 -- arch/riscv/dts/ae350_64.dts | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index b90351e87b..0917b83108 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -135,7 +135,6 @@ plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; - #address-cells = <1>; #interrupt-cells = <1>; interrupt-controller; reg = <0xe4000000 0x2000000>; @@ -148,7 +147,6 @@ plic1: interrupt-controller@e6400000 { compatible = "riscv,plic1"; - #address-cells = <1>; #interrupt-cells = <1>; interrupt-controller; reg = <0xe6400000 0x400000>; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 27ac21c716..564e94a1db 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -135,7 +135,6 @@ plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; - #address-cells = <2>; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe4000000 0x0 0x2000000>; @@ -148,7 +147,6 @@ plic1: interrupt-controller@e6400000 { compatible = "riscv,plic1"; - #address-cells = <2>; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe6400000 0x0 0x400000>;