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[v2,09/11] k210: dts: Set PLL1 to the same rate as PLL0

Message ID 20210604035834.625772-10-seanga2@gmail.com
State Superseded
Delegated to: Andes
Headers show
Series clk: k210: Rewrite K210 clock without CCF | expand

Commit Message

Sean Anderson June 4, 2021, 3:58 a.m. UTC
Linux has had some stability issues when using AISRAM with a different
frequency from SRAM. Mirror their change here now that we relocate into
AISRAM.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
---

(no changes since v1)

 arch/riscv/dts/k210.dtsi | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 2492af8038..8bcd3cebde 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -501,6 +501,8 @@ 
 					#clock-cells = <1>;
 					compatible = "kendryte,k210-clk";
 					clocks = <&in0>;
+					assigned-clocks = <&sysclk K210_CLK_PLL1>;
+					assigned-clock-rates = <390000000>;
 					u-boot,dm-pre-reloc;
 				};