From patchwork Fri Apr 23 16:27:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gerlach X-Patchwork-Id: 1469664 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=rf1O7n1X; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FRfq14jMSz9sVq for ; Sat, 24 Apr 2021 02:28:13 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AEAA682CDB; Fri, 23 Apr 2021 18:27:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="rf1O7n1X"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A4BCD82CDE; Fri, 23 Apr 2021 18:27:56 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A386782CC8 for ; Fri, 23 Apr 2021 18:27:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=d-gerlach@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 13NGRmVn050059; Fri, 23 Apr 2021 11:27:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1619195268; bh=RSz4IVr6qFkffoM/a27exVjjS9reP3ypwfAHo6NYl4U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rf1O7n1X/KoK+YtSav0yI6LAGLx8n7mL8bTS4K8vrt7OeOmXDDSwytgn4HYmLIMXg hEX3F4ugWh1O9dls6V14GD2HhF24jHQ+EfGYJjKBZMssnGvVC3FFqhZr97JwJk9/46 gvg7mmHBW0dBKz5W458D9VOAaAZCWzXQEodFuzqg= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 13NGRmJo117972 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 23 Apr 2021 11:27:48 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 23 Apr 2021 11:27:48 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Fri, 23 Apr 2021 11:27:48 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 13NGRmPg086148; Fri, 23 Apr 2021 11:27:48 -0500 From: Dave Gerlach To: , Lokesh Vutla , Tom Rini CC: Praneeth Bajjuri , Dave Gerlach , Keerthy J , Suman Anna Subject: [PATCH 03/17] arm: mach-k3: am642: Unlock all applicable control MMR registers Date: Fri, 23 Apr 2021 11:27:34 -0500 Message-ID: <20210423162748.1952-4-d-gerlach@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210423162748.1952-1-d-gerlach@ti.com> References: <20210423162748.1952-1-d-gerlach@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean To access various control MMR functionality the registers need to be unlocked. Do that for all control MMR regions in the MAIN domain. Signed-off-by: Dave Gerlach --- arch/arm/mach-k3/am642_init.c | 16 ++++++++++++++++ arch/arm/mach-k3/include/mach/am64_hardware.h | 10 ++++++---- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c index e63275ccc68f..5ab2904c5e0c 100644 --- a/arch/arm/mach-k3/am642_init.c +++ b/arch/arm/mach-k3/am642_init.c @@ -15,12 +15,28 @@ #if defined(CONFIG_SPL_BUILD) +static void ctrl_mmr_unlock(void) +{ + /* Unlock all PADCFG_MMR1 module registers */ + mmr_unlock(PADCFG_MMR1_BASE, 1); + + /* Unlock all CTRL_MMR0 module registers */ + mmr_unlock(CTRL_MMR0_BASE, 0); + mmr_unlock(CTRL_MMR0_BASE, 1); + mmr_unlock(CTRL_MMR0_BASE, 2); + mmr_unlock(CTRL_MMR0_BASE, 3); + mmr_unlock(CTRL_MMR0_BASE, 5); + mmr_unlock(CTRL_MMR0_BASE, 6); +} + void board_init_f(ulong dummy) { #if defined(CONFIG_CPU_V7R) setup_k3_mpu_regions(); #endif + ctrl_mmr_unlock(); + /* Init DM early */ spl_early_init(); diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index 8136585bde6f..ec5387025b98 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -12,6 +12,8 @@ #define CTRL_MMR0_BASE 0x43000000 #define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) +#define PADCFG_MMR1_BASE 0xf0000 + #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 @@ -29,14 +31,14 @@ #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04 /* - * The CTRL_MMR memory space is divided into several equally-spaced - * partitions, so defining the partition size allows us to determine - * register addresses common to those partitions. + * The CTRL_MMR and PADCFG_MMR memory space is divided into several + * equally-spaced partitions, so defining the partition size allows us to + * determine register addresses common to those partitions. */ #define CTRL_MMR0_PARTITION_SIZE 0x4000 /* - * CTRL_MMR lock/kick-mechanism shared register definitions. + * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions. */ #define CTRLMMR_LOCK_KICK0 0x01008 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490