| Message ID | 20210415084518.120625-2-green.wan@sifive.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | arch: riscv: cpu: Add callback to init each core | expand |
> From: Green Wan [mailto:green.wan@sifive.com] > Sent: Thursday, April 15, 2021 4:45 PM > Cc: Green Wan; Rick Jian-Zhi Chen(陳建志); Sean Anderson; Bin Meng; Simon Glass; Pragnesh Patel; Jagan Teki; Atish Patra; Leo Yu-Chi Liang(梁育齊); Brad Kim; u-boot@lists.denx.de > Subject: [RFC PATCH v6 1/2] arch: riscv: cpu: Add callback to init each core nitpicky, arch is redundant in title. riscv: cpu: Add callback to init each core will be fine. > > Add a callback harts_early_init() to start.S to allow different riscv > hart perform setup code for each hart as early as possible. Since all > the harts enter the callback, they must be able to run the same > setup. > > Signed-off-by: Green Wan <green.wan@sifive.com> > --- > arch/riscv/cpu/cpu.c | 11 +++++++++++ > arch/riscv/cpu/start.S | 8 ++++++++ > 2 files changed, 19 insertions(+) > > diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c > index 85592f5bee..43c086ca19 100644 > --- a/arch/riscv/cpu/cpu.c > +++ b/arch/riscv/cpu/cpu.c > @@ -140,3 +140,14 @@ int arch_early_init_r(void) > { > return riscv_cpu_probe(); > } > + > +/** > + * harts_early_init() - A callback function called by start.S to configure > + * feature settings of each hart. > + * > + * In a multi-core system, memory access shall be careful here, it shall > + * take care race conditions. > + */ > +__weak void harts_early_init(void) > +{ > +} > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > index 8589509e01..42fc1a4406 100644 > --- a/arch/riscv/cpu/start.S > +++ b/arch/riscv/cpu/start.S > @@ -117,6 +117,14 @@ call_board_init_f_0: > mv sp, a0 > #endif > > +#if CONFIG_IS_ENABLED(RISCV_MMODE) This M-mode check can be remove, it is a repeat confirmation in harts_early_init() of arch/riscv/cpu/fu740/spl.c Other than that, Reviewed-by: Rick Chen <rick@andestech.com> > + /* > + * Configure proprietary settings and customized CRSs of harts > + */ > +call_harts_early_init: > + jal harts_early_init > +#endif > + > #ifndef CONFIG_XIP > /* > * Pick hart to initialize global data and run U-Boot. The other harts > -- > 2.31.0
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 85592f5bee..43c086ca19 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -140,3 +140,14 @@ int arch_early_init_r(void) { return riscv_cpu_probe(); } + +/** + * harts_early_init() - A callback function called by start.S to configure + * feature settings of each hart. + * + * In a multi-core system, memory access shall be careful here, it shall + * take care race conditions. + */ +__weak void harts_early_init(void) +{ +} diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 8589509e01..42fc1a4406 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -117,6 +117,14 @@ call_board_init_f_0: mv sp, a0 #endif +#if CONFIG_IS_ENABLED(RISCV_MMODE) + /* + * Configure proprietary settings and customized CRSs of harts + */ +call_harts_early_init: + jal harts_early_init +#endif + #ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts
Add a callback harts_early_init() to start.S to allow different riscv hart perform setup code for each hart as early as possible. Since all the harts enter the callback, they must be able to run the same setup. Signed-off-by: Green Wan <green.wan@sifive.com> --- arch/riscv/cpu/cpu.c | 11 +++++++++++ arch/riscv/cpu/start.S | 8 ++++++++ 2 files changed, 19 insertions(+)