diff mbox series

[19/37] arm: imx8ulp: Enable full L2 cache in SPL

Message ID 20210412121306.11484-20-peng.fan@oss.nxp.com
State Awaiting Upstream
Delegated to: Stefano Babic
Headers show
Series imx: add i.MX8ULP support | expand

Commit Message

Peng Fan (OSS) April 12, 2021, 12:12 p.m. UTC
From: Ye Li <ye.li@nxp.com>

SRAM2 is half L2 cache and default to SRAM after system boot.
To enable the full l2 cache (512KB), it needs to reset A35 to make
the change happen.

So re-implement the jump entry function in SPL:
1. configure the core0 reset vector to entry (ATF)
2. enable the L2 full cache
3. reset A35
So when core0 up, it runs into ATF. And we have 512KB L2 cache working.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8ulp/imx-regs.h |  2 ++
 arch/arm/mach-imx/imx8ulp/soc.c              | 34 ++++++++++++++++++++
 2 files changed, 36 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index 9f76bc85fc..29b87121ea 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -20,6 +20,8 @@ 
 
 #define WDG3_RBASE		0x292a0000UL
 
+#define SIM1_BASE_ADDR 0x29290000
+
 #define CGC1_SOSCDIV_ADDR	0x292C0108
 #define CGC1_FRODIV_ADDR	0x292C0208
 
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 8f34eccfc2..be7d3d7259 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -9,6 +9,8 @@ 
 #include <asm/arch/sys_proto.h>
 #include <asm/armv8/mmu.h>
 #include <asm/mach-imx/boot_mode.h>
+#include <efi_loader.h>
+#include <spl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -289,3 +291,35 @@  int arch_cpu_init(void)
 
 	return 0;
 }
+
+#if defined(CONFIG_SPL_BUILD)
+__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	debug("image entry point: 0x%lx\n", spl_image->entry_point);
+
+	/* Update SIM1 DGO8 for reset vector base */
+	writel((u32)spl_image->entry_point, SIM1_BASE_ADDR + 0x5c);
+
+	/* set update bit */
+	setbits_le32(SIM1_BASE_ADDR + 0x8, 0x1 << 24);
+
+	/* polling the ack */
+	while ((readl(SIM1_BASE_ADDR + 0x8) & (0x1 << 26)) == 0)
+		;
+
+	/* clear the update */
+	clrbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 24));
+
+	/* clear the ack by set 1 */
+	setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
+
+	/* Enable the 512KB cache */
+	setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 4));
+
+	/* reset core */
+	setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 16));
+
+	while (1)
+		;
+}
+#endif