From patchwork Sun Apr 11 07:39:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464756 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=ZpGmcvXa; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FJ3jm0zPNz9sVq for ; Sun, 11 Apr 2021 17:42:20 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 587FA81743; Sun, 11 Apr 2021 09:41:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="ZpGmcvXa"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6A561804CB; Sun, 11 Apr 2021 09:40:31 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,RCVD_IN_SORBS_WEB,SPF_HELO_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-17-i2.italiaonline.it [213.209.12.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4710F80515 for ; Sun, 11 Apr 2021 09:40:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id VUhRl81nvtpGHVUhblpdoe; Sun, 11 Apr 2021 09:40:16 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1618126816; bh=5+Aq8mZ3irk1lz5Y7dX9XTIpH2+e42wRuMEaJPq+ctk=; h=From; b=ZpGmcvXajgOFDGb3bNi6FrYzTj5AP6Nq2aVeejkKdktebH/LP/dE7YWxwQ9gx8kL7 9VrO9nRGcZ53anIuek6Y3xn5HuWIMDmnBvF82tuq2OezY1s8UKMuCrlH3GCuX4i+f9 CLSaTHsLfiE1sqWMy7OuUTK/JFI4R7nTSTjAAqacheOZp5JeoR0xrwgZlyP9Xna/8x O2raGgzbwh8ar2BwTpRHj7IcNhmXvS9WMNcfhI7rVvpNBizxIW/aOUVuulJRqZLO1V U8k/hfQaBB3BHHGNH7GLxWJ0pOCK5StAGtRMhB3uFfYDD+M6+207dPZKRoZnzbGCsv VX6vK/L1BY9Vw== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6072a7e0 cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=cm27Pg_UAAAA:8 a=SHmA3wKN3BWJ4-rrrCYA:9 a=xmb-EsYY8bH0VWELuYED:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v4 08/12] pinctrl: single: add register access functions Date: Sun, 11 Apr 2021 09:39:46 +0200 Message-Id: <20210411073950.24772-9-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210411073950.24772-1-dariobin@libero.it> References: <20210411073950.24772-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfJeFOC3wnkZFiUr2qTHw5JMymSOI2yZ+FXrasjDnR0uizUpJmhSlNYuPHDtl6CKN+0dgO9SjCmAii/UJvgsitF8aKA7EokAxBI9X4XkhJkVSAE/ZAhTF /QMa2KHhWD1YN6av3csje/xsU68Rko6O/0nkgUACcyzT1OZVmmgbn+ogeF49vJsH6M1IH0XE4DN+kKeB5zCR+KeGOdULJ+4v9uLMliR3jrcN9ACDdb1If/3W O+atmTZwSruTWP+c8V89z211ROomOP+EDuYenBsm6t4bk1LruH/HHaH+87WzxypRX4bsFlOcIY9zXMeeCWqRQHJWVQPrghmPD7XMfPTUOaH+WkqsDkA3ejgK IInnXGNYpwfzdcPx7OlXve60Jb9PYQ== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The configuration of pinmux registers was implemented with duplicate code which can be removed by adding two functions for read/write access. Access to 8-bit registers has also been added. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- (no changes since v3) Changes in v3: - Added Simon Glass review tag. Changes in v2: - Updated commit message. - Remove pointer to access functions. drivers/pinctrl/pinctrl-single.c | 71 +++++++++++++++++++++----------- 1 file changed, 46 insertions(+), 25 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 630a6c08b8..5b3ccc2281 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -56,6 +56,38 @@ struct single_fdt_bits_cfg { fdt32_t mask; }; +static unsigned int single_read(struct udevice *dev, fdt_addr_t reg) +{ + struct single_pdata *pdata = dev_get_plat(dev); + + switch (pdata->width) { + case 8: + return readb(reg); + case 16: + return readw(reg); + default: /* 32 bits */ + return readl(reg); + } + + return readb(reg); +} + +static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg) +{ + struct single_pdata *pdata = dev_get_plat(dev); + + switch (pdata->width) { + case 8: + writeb(val, reg); + break; + case 16: + writew(val, reg); + break; + default: /* 32 bits */ + writel(val, reg); + } +} + /** * single_configure_pins() - Configure pins based on FDT data * @@ -93,19 +125,10 @@ static int single_configure_pins(struct udevice *dev, reg = pdata->base + offset; val = fdt32_to_cpu(pins->val) & pdata->mask; - switch (pdata->width) { - case 16: - writew((readw(reg) & ~pdata->mask) | val, reg); - break; - case 32: - writel((readl(reg) & ~pdata->mask) | val, reg); - break; - default: - dev_warn(dev, "unsupported register width %i\n", - pdata->width); - continue; - } + single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val, + reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); + } return 0; } @@ -131,19 +154,7 @@ static int single_configure_bits(struct udevice *dev, mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask; - - switch (pdata->width) { - case 16: - writew((readw(reg) & ~mask) | val, reg); - break; - case 32: - writel((readl(reg) & ~mask) | val, reg); - break; - default: - dev_warn(dev, "unsupported register width %i\n", - pdata->width); - continue; - } + single_write(dev, (single_read(dev, reg) & ~mask) | val, reg); dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val); } return 0; @@ -196,6 +207,16 @@ static int single_of_to_plat(struct udevice *dev) return ret; } + switch (pdata->width) { + case 8: + case 16: + case 32: + break; + default: + dev_err(dev, "wrong register width\n"); + return -EINVAL; + } + addr = dev_read_addr_size(dev, "reg", &size); if (addr == FDT_ADDR_T_NONE) { dev_err(dev, "failed to get base register size\n");