From patchwork Sun Apr 11 07:39:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1464752 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2021 header.b=ay8OWbEx; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FJ3hh5hDBz9sVq for ; Sun, 11 Apr 2021 17:41:24 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EDA7681578; Sun, 11 Apr 2021 09:40:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="ay8OWbEx"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id CD16B80484; Sun, 11 Apr 2021 09:40:24 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM, RCVD_IN_SORBS_WEB,SPF_HELO_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-17.italiaonline.it [213.209.10.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C561D804B3 for ; Sun, 11 Apr 2021 09:40:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id VUhRl81nvtpGHVUhZlpdne; Sun, 11 Apr 2021 09:40:13 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1618126813; bh=yWhdoUJKRp2th0HecPQIEXplkalTulfUaCnVgtbEfPk=; h=From; b=ay8OWbExqNeBsFiJugdiBqlc6fGXZbwgQck3URpfmu/v050/cLSSdKsEAaZiL93Ik WOsvBeToN1kSMO13MWAzd86vpQvC29m5voVjiGzSW86Z5M4HwWPtH3kZ9iwebKiSzw 7gkedyQ4gfD/VY4b2l2Y0Q37UrgVVYUbArqM0PbW+Bmwu5Fxjk6/Le2yyRHTrxNG0+ XsEKQ/c046O3/+GSHtB8/JgMMSs8tFl02QCuKKzsBmKVXNlP1JLtRcOeW9oCOngSTk 8fsMCxG3DL1FRxDfvAjweQMDSd14YIp2KSP1YTeq1VYab6v6kxUph2IMI25OE+j/Nc RABk9428jfAVQ== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6072a7dd cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=sozttTNsAAAA:8 a=wv_ar1DUYrJP48xX2MwA:9 a=aeg5Gbbo78KNqacMgKqU:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Pratyush Yadav , Simon Glass Subject: [PATCH v4 03/12] pinctrl: single: fix offset management Date: Sun, 11 Apr 2021 09:39:41 +0200 Message-Id: <20210411073950.24772-4-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210411073950.24772-1-dariobin@libero.it> References: <20210411073950.24772-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfD33vhLSjuNxfUwRQ9tvS5sPQSgppOjLqVYk2b/dzNJf8TvmiERjoolqiDxs2WrPYwBxobpNrYu7Pb2CP/Dkdi6aKW0nqULM4KblmfLsgPJgEJsNI06P T9a6wN8kdSYXnvw4WpR9L+S26Ac89KGDGTf5OId0nWGBg6Oe8kuwu9iPnc2FNVs72rZBDoN5w8u2F6ke2PNUgMG85Q9fLrguXg7HfZJ6iaCeH0ozV9DJKOMp h/BM5++zmpEtTGQ0ri5fj/wdou68e21u8s9ZGBFYeOLj0MXUy5VnisPAG+0m2RYPYm/PrItw8JJ7bZ5IfwnEfCWOA0I1wGo34rOn35PBG9N1j7QnrAnb/EI2 kFJZosEY0mYKspSDIVMrL0cCKLIZzbqLLsyF6FlLc/ZA2DiWQxFWUgkOGSEEjIcxxvW5bghWLueLheftKy5TqnKnGJlcSA== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The pinmux configuration DT node of a peripheral does not define a physical address but an offset. Only by adding it to the base address of the controller it is possible to calculate the physical address of the register to be configured. Printing an offset also requires a different formatting option than a physical address. Signed-off-by: Dario Binacchi Reviewed-by: Pratyush Yadav --- (no changes since v3) Changes in v3: - Added Pratyush Yadav review tag. drivers/pinctrl/pinctrl-single.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 49ed15211d..935b5e920d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -77,15 +77,17 @@ static int single_configure_pins(struct udevice *dev, struct single_pdata *pdata = dev_get_plat(dev); int n, count = size / sizeof(struct single_fdt_pin_cfg); phys_addr_t reg; - u32 val; + u32 offset, val; for (n = 0; n < count; n++, pins++) { - reg = fdt32_to_cpu(pins->reg); - if ((reg < 0) || (reg > pdata->offset)) { - dev_dbg(dev, " invalid register offset 0x%pa\n", ®); + offset = fdt32_to_cpu(pins->reg); + if (offset < 0 || offset > pdata->offset) { + dev_dbg(dev, " invalid register offset 0x%x\n", + offset); continue; } - reg += pdata->base; + + reg = pdata->base + offset; val = fdt32_to_cpu(pins->val) & pdata->mask; switch (pdata->width) { case 16: @@ -111,15 +113,17 @@ static int single_configure_bits(struct udevice *dev, struct single_pdata *pdata = dev_get_plat(dev); int n, count = size / sizeof(struct single_fdt_bits_cfg); phys_addr_t reg; - u32 val, mask; + u32 offset, val, mask; for (n = 0; n < count; n++, pins++) { - reg = fdt32_to_cpu(pins->reg); - if ((reg < 0) || (reg > pdata->offset)) { - dev_dbg(dev, " invalid register offset 0x%pa\n", ®); + offset = fdt32_to_cpu(pins->reg); + if (offset < 0 || offset > pdata->offset) { + dev_dbg(dev, " invalid register offset 0x%x\n", + offset); continue; } - reg += pdata->base; + + reg = pdata->base + offset; mask = fdt32_to_cpu(pins->mask); val = fdt32_to_cpu(pins->val) & mask;