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[v1,05/23] phy: marvell: cp110: utmi: update analog parameters according to latest ETP

Message ID 20210324150325.v1.5.I5bcca205a3995202a18ff126f371a81f69e205c8@changeid
State Accepted
Commit 3e69b4abffdd2b11b9d382e3a21414d6b7640efe
Delegated to: Stefan Roese
Headers show
Series phy: marvell: Sync Armada 3k/7k/8k SERDES code with Marvell version | expand

Commit Message

Stefan Roese March 24, 2021, 2:06 p.m. UTC 
From: Igal Liberman <igall@marvell.com>

Add UTMI analog parameters initialization values according to
latest ETP.

Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---

 drivers/phy/marvell/comphy_cp110.c | 9 +++------
 drivers/phy/marvell/utmi_phy.h     | 5 ++++-
 2 files changed, 7 insertions(+), 7 deletions(-)
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Patch

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 82d869368858..72563f8bc1c5 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -614,15 +614,12 @@  static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
 
 	/* Impedance Calibration Threshold Setting */
 	reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG,
-		0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
+		0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
 		UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
 
 	/* Set LS TX driver strength coarse control */
-	mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
-	data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
-	/* Set LS TX driver fine adjustment */
-	mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
-	data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
+	mask = UTMI_TX_CH_CTRL_AMP_MASK;
+	data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET;
 	reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
 
 	/* Enable SQ */
diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h
index 682a3acc40d8..fa6bf3c9141e 100644
--- a/drivers/phy/marvell/utmi_phy.h
+++ b/drivers/phy/marvell/utmi_phy.h
@@ -52,6 +52,9 @@ 
 #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET	16
 #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK		\
 	(0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET)
+#define UTMI_TX_CH_CTRL_AMP_OFFSET		20
+#define UTMI_TX_CH_CTRL_AMP_MASK		\
+	(0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)
 
 #define UTMI_RX_CH_CTRL0_REG			0x14
 #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET		15
@@ -64,7 +67,7 @@ 
 #define UTMI_RX_CH_CTRL1_REG			0x18
 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET	0
 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK	\
-	(0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
+	(0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET	3
 #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK	\
 	(0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)