From patchwork Wed Mar 24 14:06:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 1457906 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=c9mLLjvG; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F59851bSRz9sRR for ; Thu, 25 Mar 2021 01:08:53 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5A95182822; Wed, 24 Mar 2021 15:07:55 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1616594875; bh=Pb74JZ0A4vL1jlyFGy5oU5a8+C6VbKW7VBG5AwBfU+U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=c9mLLjvGECgCusSQhizCjZ671k+QcYkIlvLy4O6TzL4Ltp2yK7EHwov55hSfkAx3m z4rO1GMlF8zNwV21kTWaBKhmwbCTDoHM5YMViUETwOpTmtvlKbdsYo2DR37+B8S391 /tGXv65dV33ya2N7SQ15JVvI7FDQrwaNFMEEFcU9DevGE5KuwoYvdmtdqmLC9FCIri q3YnOE3G4iletnKNk2N6EjnI2VVYphUst9bh2cismgoLLtclR880ORoJI4vOCCdn/X bS9AhN/q6bKZaWPD9cExIqY7mk2CIQ6LnpCjzQfDwsWQBet/yhzhq9/CM/fWyINtZF ER59eUbSDh8dA== Received: by phobos.denx.de (Postfix, from userid 109) id 5082082822; Wed, 24 Mar 2021 15:07:14 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [IPv6:2001:67c:2050:1::465:204]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 343598280D for ; Wed, 24 Mar 2021 15:07:00 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:105:465:1:2:0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4F595v6jM4zQjpM; Wed, 24 Mar 2021 15:06:59 +0100 (CET) Received: from smtp2.mailbox.org ([80.241.60.241]) by hefe.heinlein-support.de (hefe.heinlein-support.de [91.198.250.172]) (amavisd-new, port 10030) with ESMTP id jySx_pstmSTh; Wed, 24 Mar 2021 15:06:56 +0100 (CET) From: Stefan Roese To: u-boot@lists.denx.de Cc: Nadav Haklai , =?utf-8?q?Pali_Roh=C3=A1r?= , Kostya Porotchkin , =?utf-8?q?Marek_Beh=C3=BAn?= , Grzegorz Jaszczyk , Igal Liberman , Baruch Siach Subject: [PATCH v1 12/23] phy: marvell: cp110: let the firmware configure comphy for USB Date: Wed, 24 Mar 2021 15:06:38 +0100 Message-Id: <20210324150325.v1.12.I7f773c0dfac70db9dd2653de2cdcfac577e78c4e@changeid> In-Reply-To: <20210324140649.1413122-1-sr@denx.de> References: <20210324140649.1413122-1-sr@denx.de> MIME-Version: 1.0 X-MBO-SPAM-Probability: X-Rspamd-Score: -1.04 / 15.00 / 15.00 X-Rspamd-Queue-Id: B932F181B X-Rspamd-UID: 6a15aa X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: Grzegorz Jaszczyk Replace the comphy initialization for USB with appropriate SMC call, so the firmware will execute required serdes configuration. Signed-off-by: Grzegorz Jaszczyk Signed-off-by: Stefan Roese --- drivers/phy/marvell/comphy_cp110.c | 133 ++--------------------------- 1 file changed, 9 insertions(+), 124 deletions(-) diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 9f80a3fda4b1..cbfc89cb0c36 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -323,128 +323,6 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, return ret; } -static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, - void __iomem *comphy_base) -{ - u32 mask, data, ret = 1; - void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); - void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); - void __iomem *addr; - - debug_enter(); - debug("stage: RFU configurations - hard reset comphy\n"); - /* RFU configurations - hard reset comphy */ - mask = COMMON_PHY_CFG1_PWR_UP_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; - data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - mask |= COMMON_PHY_PHY_MODE_MASK; - data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - /* release from hard reset */ - mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); - - /* Wait 1ms - until band gap and ref clock ready */ - mdelay(1); - - /* Start comphy Configuration */ - debug("stage: Comphy configuration\n"); - /* Set PIPE soft reset */ - mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; - data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; - /* Set PHY datapath width mode for V0 */ - mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; - data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; - /* Set Data bus width USB mode for V0 */ - mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; - data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; - /* Set CORE_CLK output frequency for 250Mhz */ - mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; - data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; - reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); - /* Set PLL ready delay for 0x2 */ - reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, - 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, - HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); - /* Set reference clock to come from group 1 - 25Mhz */ - reg_set(hpipe_addr + HPIPE_MISC_REG, - 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, - HPIPE_MISC_REFCLK_SEL_MASK); - /* Set reference frequcency select - 0x2 */ - mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - /* Set PHY mode to USB - 0x5 */ - mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; - data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); - /* Set the amount of time spent in the LoZ state - set for 0x7 */ - reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL, - 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, - HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); - /* Set max PHY generation setting - 5Gbps */ - reg_set(hpipe_addr + HPIPE_INTERFACE_REG, - 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, - HPIPE_INTERFACE_GEN_MAX_MASK); - /* Set select data width 20Bit (SEL_BITS[2:0]) */ - reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, - 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, - HPIPE_LOOPBACK_SEL_MASK); - /* select de-emphasize 3.5db */ - reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG, - 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET, - HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK); - /* override tx margining from the MAC */ - reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG, - 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET, - HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK); - - /* Start analog paramters from ETP(HW) */ - debug("stage: Analog paramters from ETP(HW)\n"); - /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ - mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; - data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; - /* Set Override PHY DFE control pins for 0x1 */ - mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; - data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; - /* Set Spread Spectrum Clock Enable fot 0x1 */ - mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; - data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; - reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); - /* End of analog parameters */ - - debug("stage: Comphy power up\n"); - /* Release from PIPE soft reset */ - reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); - - /* wait 15ms - for comphy calibration done */ - debug("stage: Check PLL\n"); - /* Read lane status */ - addr = hpipe_addr + HPIPE_LANE_STATUS1_REG; - data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; - mask = data; - data = polling_with_timeout(addr, data, mask, 15000); - if (data != 0) { - debug("Read from reg = %p - value = 0x%x\n", - hpipe_addr + HPIPE_LANE_STATUS1_REG, data); - pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n"); - ret = 0; - } - - debug_exit(); - return ret; -} - static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr, u32 lane, u32 mode) { @@ -960,9 +838,16 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, break; case COMPHY_TYPE_USB3_HOST0: case COMPHY_TYPE_USB3_HOST1: + mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE); + ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, + ptr_chip_cfg->comphy_base_addr, lane, + mode); + break; case COMPHY_TYPE_USB3_DEVICE: - ret = comphy_usb3_power_up(lane, hpipe_base_addr, - comphy_base_addr); + mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE); + ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, + ptr_chip_cfg->comphy_base_addr, lane, + mode); break; case COMPHY_TYPE_SGMII0: case COMPHY_TYPE_SGMII1: