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[v2,17/19] video: dw-hdmi: modify phy init callback to include full timings

Message ID 20210306195437.9740-18-jernej.skrabec@siol.net
State Under Review
Delegated to: Andre Przywara
Headers show
Series video: sunxi: rework DE2 driver | expand

Commit Message

Jernej Škrabec March 6, 2021, 7:54 p.m. UTC
Currently PHY init callback has only pixel clock as a parameter, but
other timing parameters may be needed for custom PHYs. Modify callback
signature to include full timings.

Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/video/dw_hdmi.c             | 6 +++---
 drivers/video/meson/meson_dw_hdmi.c | 5 +++--
 drivers/video/sunxi/sunxi_dw_hdmi.c | 7 ++++---
 include/dw_hdmi.h                   | 4 ++--
 4 files changed, 12 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c
index c4fbb1829446..8d71f713f99f 100644
--- a/drivers/video/dw_hdmi.c
+++ b/drivers/video/dw_hdmi.c
@@ -901,7 +901,7 @@  static const u8 pre_buf[] = {
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
 };
 
-int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
+int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, const struct display_timing *edid)
 {
 	int i, ret;
 
@@ -912,7 +912,7 @@  int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
 		hdmi_phy_enable_tmds(hdmi, 0);
 		hdmi_phy_enable_power(hdmi, 0);
 
-		ret = hdmi_phy_configure(hdmi, mpixelclock);
+		ret = hdmi_phy_configure(hdmi, edid->pixelclock.typ);
 		if (ret) {
 			debug("hdmi phy config failure %d\n", ret);
 			return ret;
@@ -988,7 +988,7 @@  int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
 
 	hdmi_av_composer(hdmi, edid);
 
-	ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
+	ret = hdmi->phy_set(hdmi, edid);
 	if (ret)
 		return ret;
 
diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c
index e5f281320534..7558814b3491 100644
--- a/drivers/video/meson/meson_dw_hdmi.c
+++ b/drivers/video/meson/meson_dw_hdmi.c
@@ -292,7 +292,8 @@  static void meson_dw_hdmi_phy_setup_mode(struct meson_dw_hdmi *priv,
 	}
 }
 
-static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock)
+static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi,
+				  const struct display_timing *edid)
 {
 	struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,
 						  hdmi);
@@ -322,7 +323,7 @@  static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock)
 	dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
 
 	/* Setup PHY parameters */
-	meson_dw_hdmi_phy_setup_mode(priv, pixel_clock);
+	meson_dw_hdmi_phy_setup_mode(priv, edid->pixelclock.typ);
 
 	/* Setup PHY */
 	dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1,
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 0744954fa15f..483d57293155 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -266,12 +266,13 @@  static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
 	lcdc_enable(lcdc, bpp);
 }
 
-static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
+static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi,
+				 const struct display_timing *edid)
 {
 	int phy_div;
 
-	sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
-	sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div);
+	sunxi_dw_hdmi_pll_set(edid->pixelclock.typ / 1000, &phy_div);
+	sunxi_dw_hdmi_phy_set(hdmi, edid->pixelclock.typ, phy_div);
 
 	return 0;
 }
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
index 8acae3839fb3..46b87916b8bb 100644
--- a/include/dw_hdmi.h
+++ b/include/dw_hdmi.h
@@ -544,12 +544,12 @@  struct dw_hdmi {
 	struct hdmi_data_info hdmi_data;
 	struct udevice *ddc_bus;
 
-	int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
+	int (*phy_set)(struct dw_hdmi *hdmi, const struct display_timing *edid);
 	void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset);
 	u8 (*read_reg)(struct dw_hdmi *hdmi, int offset);
 };
 
-int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);
+int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, const struct display_timing *edid);
 int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi);
 void dw_hdmi_phy_init(struct dw_hdmi *hdmi);