From patchwork Sat Mar 6 19:54:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1448504 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtFl62PNwz9sR4 for ; Sun, 7 Mar 2021 06:57:54 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F21288263A; Sat, 6 Mar 2021 20:55:47 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 522D08280F; Sat, 6 Mar 2021 20:55:23 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=no autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs48.siol.net [185.57.226.239]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 04FBE827BE for ; Sat, 6 Mar 2021 20:55:19 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id A495752270F; Sat, 6 Mar 2021 20:55:18 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta09.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id 59YKcHMYVwGA; Sat, 6 Mar 2021 20:55:18 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 56F0C522E0D; Sat, 6 Mar 2021 20:55:18 +0100 (CET) Received: from localhost.localdomain (89-212-178-211.dynamic.t-2.net [89.212.178.211]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 2AAF152270F; Sat, 6 Mar 2021 20:55:16 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com Cc: agust@denx.de, u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH v2 16/19] video: sunxi: de2: switch clock setup to DM model Date: Sat, 6 Mar 2021 20:54:34 +0100 Message-Id: <20210306195437.9740-17-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210306195437.9740-1-jernej.skrabec@siol.net> References: <20210306195437.9740-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Now that proper DM clock and reset driver exists for Display Engine 2 and 3, remove all clock and reset related code and use appropriate framework instead. Signed-off-by: Jernej Skrabec Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/Kconfig | 1 + drivers/video/sunxi/sunxi_de2.c | 67 +++++++++++---------------------- 2 files changed, 23 insertions(+), 45 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 9149196b223e..34ef1f4b030f 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -970,6 +970,7 @@ config SUNXI_DE2 config VIDEO_DE2 bool "Display Engine 2 video driver" depends on SUNXI_DE2 + select CLK_SUN8I_DE2 select DM_VIDEO select DISPLAY select VIDEO_DW_HDMI diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index f6c8ca075aba..cee9b46b1259 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -14,10 +15,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include "simplefb_common.h" @@ -36,40 +37,10 @@ struct sunxi_de2_data { const char *disp_drv_name; }; -static void sunxi_de2_composer_init(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - -#ifdef CONFIG_MACH_SUN50I - u32 reg_value; - - /* set SRAM for video use (A64 only) */ - reg_value = readl(SUNXI_SRAMC_BASE + 0x04); - reg_value &= ~(0x01 << 24); - writel(reg_value, SUNXI_SRAMC_BASE + 0x04); -#endif - - clock_set_pll10(432000000); - - /* Set DE parent to pll10 */ - clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, - CCM_DE2_CTRL_PLL10); - - /* Set ahb gating to pass */ - setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); - setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE); - - /* Clock on */ - setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); -} - -static void sunxi_de2_mode_set(ulong de_mux_base, int mux, +static void sunxi_de2_mode_set(ulong de_mux_base, const struct display_timing *mode, int bpp, ulong address, bool is_composite) { - struct de_clk * const de_clk_regs = - (struct de_clk *)(SUNXI_DE2_BASE); struct de_glb * const de_glb_regs = (struct de_glb *)(de_mux_base + SUNXI_DE2_MUX_GLB_REGS); @@ -87,17 +58,6 @@ static void sunxi_de2_mode_set(ulong de_mux_base, int mux, int channel; u32 format; - /* enable clock */ -#ifdef CONFIG_MACH_SUN8I_H3 - setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4); -#else - setbits_le32(&de_clk_regs->rst_cfg, BIT(mux)); -#endif - setbits_le32(&de_clk_regs->gate_cfg, BIT(mux)); - setbits_le32(&de_clk_regs->bus_cfg, BIT(mux)); - - clrbits_le32(&de_clk_regs->sel_cfg, 1); - writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl); writel(0, &de_glb_regs->status); writel(1, &de_glb_regs->dbuff); @@ -189,6 +149,8 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct display_timing timing; struct display_plat *disp_uc_plat; + struct reset_ctl_bulk resets; + struct clk_bulk clocks; int ret; disp_uc_plat = dev_get_uclass_plat(disp); @@ -206,8 +168,23 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, return ret; } - sunxi_de2_composer_init(); - sunxi_de2_mode_set((ulong)dev_read_addr(dev), mux, &timing, + ret = reset_get_bulk(dev, &resets); + if (ret) + return ret; + + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + + ret = reset_deassert_bulk(&resets); + if (ret) + return ret; + + sunxi_de2_mode_set((ulong)dev_read_addr(dev), &timing, 1 << l2bpp, fbbase, is_composite); ret = display_enable(disp, 1 << l2bpp, &timing);