From patchwork Sat Mar 6 19:54:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1448499 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DtFk62msXz9sR4 for ; Sun, 7 Mar 2021 06:57:02 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6BA2F827C3; Sat, 6 Mar 2021 20:55:31 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id E43E8827E3; Sat, 6 Mar 2021 20:55:13 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=no autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs14.siol.net [185.57.226.205]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 06406827AB for ; Sat, 6 Mar 2021 20:55:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id B6FCB520EDB; Sat, 6 Mar 2021 20:55:07 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta09.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id Wu07q8g4dJPj; Sat, 6 Mar 2021 20:55:07 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 62402520F68; Sat, 6 Mar 2021 20:55:07 +0100 (CET) Received: from localhost.localdomain (89-212-178-211.dynamic.t-2.net [89.212.178.211]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 2477B520D0F; Sat, 6 Mar 2021 20:55:05 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com Cc: agust@denx.de, u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH v2 11/19] video: sunxi: dw-hdmi: read address from DT node Date: Sat, 6 Mar 2021 20:54:29 +0100 Message-Id: <20210306195437.9740-12-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210306195437.9740-1-jernej.skrabec@siol.net> References: <20210306195437.9740-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Currently HDMI controller MMIO address is hardcoded. Change that so address is read from DT node. That will make adding support for new variants a bit easier. Signed-off-by: Jernej Skrabec Reviewed-by: Andre Przywara --- drivers/video/sunxi/sunxi_dw_hdmi.c | 38 ++++++++++++++++++----------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 6f77b2a43b40..0744954fa15f 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -57,10 +57,10 @@ static int sunxi_dw_hdmi_get_divider(uint clock) return 1; } -static void sunxi_dw_hdmi_phy_init(void) +static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi) { struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); + (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); unsigned long tmo; u32 tmp; @@ -114,10 +114,10 @@ static void sunxi_dw_hdmi_phy_init(void) writel(0x42494E47, &phy->unscramble); } -static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div) +static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div) { struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); + (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); int div = sunxi_dw_hdmi_get_divider(clock); u32 tmp; @@ -271,7 +271,7 @@ static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) int phy_div; sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div); - sunxi_dw_hdmi_phy_set(mpixelclock, phy_div); + sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div); return 0; } @@ -292,9 +292,9 @@ static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev, static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, const struct display_timing *edid) { - struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); + struct sunxi_hdmi_phy * const phy = + (struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS); int ret; ret = dw_hdmi_enable(&priv->hdmi, edid); @@ -316,12 +316,26 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, * again or othwerwise BSP driver won't work. Dummy read is * needed or otherwise last write doesn't get written correctly. */ - (void)readb(SUNXI_HDMI_BASE); + (void)readb(priv->hdmi.ioaddr); writel(0, &phy->unscramble); return 0; } +static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev) +{ + struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); + struct dw_hdmi *hdmi = &priv->hdmi; + + hdmi->ioaddr = (ulong)dev_read_addr(dev); + hdmi->i2c_clk_high = 0xd8; + hdmi->i2c_clk_low = 0xfe; + hdmi->reg_io_width = 1; + hdmi->phy_set = sunxi_dw_hdmi_phy_cfg; + + return 0; +} + static int sunxi_dw_hdmi_probe(struct udevice *dev) { struct display_plat *uc_plat = dev_get_uclass_plat(dev); @@ -346,13 +360,8 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) /* Clock on */ setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); - sunxi_dw_hdmi_phy_init(); + sunxi_dw_hdmi_phy_init(&priv->hdmi); - priv->hdmi.ioaddr = SUNXI_HDMI_BASE; - priv->hdmi.i2c_clk_high = 0xd8; - priv->hdmi.i2c_clk_low = 0xfe; - priv->hdmi.reg_io_width = 1; - priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg; priv->mux = uc_plat->source_id; ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi); @@ -382,6 +391,7 @@ U_BOOT_DRIVER(sunxi_dw_hdmi) = { .id = UCLASS_DISPLAY, .of_match = sunxi_dw_hdmi_ids, .ops = &sunxi_dw_hdmi_ops, + .of_to_plat = sunxi_dw_hdmi_of_to_plat, .probe = sunxi_dw_hdmi_probe, .priv_auto = sizeof(struct sunxi_dw_hdmi_priv), };