diff mbox series

[v2,11/19] video: sunxi: dw-hdmi: read address from DT node

Message ID 20210306195437.9740-12-jernej.skrabec@siol.net
State Under Review
Delegated to: Andre Przywara
Headers show
Series video: sunxi: rework DE2 driver | expand

Commit Message

Jernej Škrabec March 6, 2021, 7:54 p.m. UTC
Currently HDMI controller MMIO address is hardcoded. Change that so
address is read from DT node. That will make adding support for new
variants a bit easier.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/video/sunxi/sunxi_dw_hdmi.c | 38 ++++++++++++++++++-----------
 1 file changed, 24 insertions(+), 14 deletions(-)

Comments

Andre Przywara April 6, 2021, 1:09 a.m. UTC | #1
On Sat,  6 Mar 2021 20:54:29 +0100
Jernej Skrabec <jernej.skrabec@siol.net> wrote:

> Currently HDMI controller MMIO address is hardcoded. Change that so
> address is read from DT node. That will make adding support for new
> variants a bit easier.
> 
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>

Checked the transformations, and it's still working (after fixing the
mux problem with your new patch in your github).

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Thanks,
Andre

> ---
>  drivers/video/sunxi/sunxi_dw_hdmi.c | 38 ++++++++++++++++++-----------
>  1 file changed, 24 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
> index 6f77b2a43b40..0744954fa15f 100644
> --- a/drivers/video/sunxi/sunxi_dw_hdmi.c
> +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
> @@ -57,10 +57,10 @@ static int sunxi_dw_hdmi_get_divider(uint clock)
>  		return 1;
>  }
>  
> -static void sunxi_dw_hdmi_phy_init(void)
> +static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi)
>  {
>  	struct sunxi_hdmi_phy * const phy =
> -		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
> +		(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
>  	unsigned long tmo;
>  	u32 tmp;
>  
> @@ -114,10 +114,10 @@ static void sunxi_dw_hdmi_phy_init(void)
>  	writel(0x42494E47, &phy->unscramble);
>  }
>  
> -static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
> +static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div)
>  {
>  	struct sunxi_hdmi_phy * const phy =
> -		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
> +		(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
>  	int div = sunxi_dw_hdmi_get_divider(clock);
>  	u32 tmp;
>  
> @@ -271,7 +271,7 @@ static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
>  	int phy_div;
>  
>  	sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
> -	sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
> +	sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div);
>  
>  	return 0;
>  }
> @@ -292,9 +292,9 @@ static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev,
>  static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
>  				const struct display_timing *edid)
>  {
> -	struct sunxi_hdmi_phy * const phy =
> -		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
>  	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
> +	struct sunxi_hdmi_phy * const phy =
> +		(struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS);
>  	int ret;
>  
>  	ret = dw_hdmi_enable(&priv->hdmi, edid);
> @@ -316,12 +316,26 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
>  	 * again or othwerwise BSP driver won't work. Dummy read is
>  	 * needed or otherwise last write doesn't get written correctly.
>  	 */
> -	(void)readb(SUNXI_HDMI_BASE);
> +	(void)readb(priv->hdmi.ioaddr);
>  	writel(0, &phy->unscramble);
>  
>  	return 0;
>  }
>  
> +static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
> +{
> +	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
> +	struct dw_hdmi *hdmi = &priv->hdmi;
> +
> +	hdmi->ioaddr = (ulong)dev_read_addr(dev);
> +	hdmi->i2c_clk_high = 0xd8;
> +	hdmi->i2c_clk_low = 0xfe;
> +	hdmi->reg_io_width = 1;
> +	hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
> +
> +	return 0;
> +}
> +
>  static int sunxi_dw_hdmi_probe(struct udevice *dev)
>  {
>  	struct display_plat *uc_plat = dev_get_uclass_plat(dev);
> @@ -346,13 +360,8 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
>  	/* Clock on */
>  	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
>  
> -	sunxi_dw_hdmi_phy_init();
> +	sunxi_dw_hdmi_phy_init(&priv->hdmi);
>  
> -	priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
> -	priv->hdmi.i2c_clk_high = 0xd8;
> -	priv->hdmi.i2c_clk_low = 0xfe;
> -	priv->hdmi.reg_io_width = 1;
> -	priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
>  	priv->mux = uc_plat->source_id;
>  
>  	ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi);
> @@ -382,6 +391,7 @@ U_BOOT_DRIVER(sunxi_dw_hdmi) = {
>  	.id	= UCLASS_DISPLAY,
>  	.of_match = sunxi_dw_hdmi_ids,
>  	.ops	= &sunxi_dw_hdmi_ops,
> +	.of_to_plat = sunxi_dw_hdmi_of_to_plat,
>  	.probe	= sunxi_dw_hdmi_probe,
>  	.priv_auto	= sizeof(struct sunxi_dw_hdmi_priv),
>  };
diff mbox series

Patch

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 6f77b2a43b40..0744954fa15f 100644
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -57,10 +57,10 @@  static int sunxi_dw_hdmi_get_divider(uint clock)
 		return 1;
 }
 
-static void sunxi_dw_hdmi_phy_init(void)
+static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 {
 	struct sunxi_hdmi_phy * const phy =
-		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+		(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
 	unsigned long tmo;
 	u32 tmp;
 
@@ -114,10 +114,10 @@  static void sunxi_dw_hdmi_phy_init(void)
 	writel(0x42494E47, &phy->unscramble);
 }
 
-static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
+static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div)
 {
 	struct sunxi_hdmi_phy * const phy =
-		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
+		(struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS);
 	int div = sunxi_dw_hdmi_get_divider(clock);
 	u32 tmp;
 
@@ -271,7 +271,7 @@  static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
 	int phy_div;
 
 	sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
-	sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
+	sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div);
 
 	return 0;
 }
@@ -292,9 +292,9 @@  static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev,
 static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 				const struct display_timing *edid)
 {
-	struct sunxi_hdmi_phy * const phy =
-		(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
 	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
+	struct sunxi_hdmi_phy * const phy =
+		(struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS);
 	int ret;
 
 	ret = dw_hdmi_enable(&priv->hdmi, edid);
@@ -316,12 +316,26 @@  static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 	 * again or othwerwise BSP driver won't work. Dummy read is
 	 * needed or otherwise last write doesn't get written correctly.
 	 */
-	(void)readb(SUNXI_HDMI_BASE);
+	(void)readb(priv->hdmi.ioaddr);
 	writel(0, &phy->unscramble);
 
 	return 0;
 }
 
+static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
+{
+	struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
+	struct dw_hdmi *hdmi = &priv->hdmi;
+
+	hdmi->ioaddr = (ulong)dev_read_addr(dev);
+	hdmi->i2c_clk_high = 0xd8;
+	hdmi->i2c_clk_low = 0xfe;
+	hdmi->reg_io_width = 1;
+	hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
+
+	return 0;
+}
+
 static int sunxi_dw_hdmi_probe(struct udevice *dev)
 {
 	struct display_plat *uc_plat = dev_get_uclass_plat(dev);
@@ -346,13 +360,8 @@  static int sunxi_dw_hdmi_probe(struct udevice *dev)
 	/* Clock on */
 	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
 
-	sunxi_dw_hdmi_phy_init();
+	sunxi_dw_hdmi_phy_init(&priv->hdmi);
 
-	priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
-	priv->hdmi.i2c_clk_high = 0xd8;
-	priv->hdmi.i2c_clk_low = 0xfe;
-	priv->hdmi.reg_io_width = 1;
-	priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
 	priv->mux = uc_plat->source_id;
 
 	ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi);
@@ -382,6 +391,7 @@  U_BOOT_DRIVER(sunxi_dw_hdmi) = {
 	.id	= UCLASS_DISPLAY,
 	.of_match = sunxi_dw_hdmi_ids,
 	.ops	= &sunxi_dw_hdmi_ops,
+	.of_to_plat = sunxi_dw_hdmi_of_to_plat,
 	.probe	= sunxi_dw_hdmi_probe,
 	.priv_auto	= sizeof(struct sunxi_dw_hdmi_priv),
 };