| Message ID | 20210303133759.16397-1-pali@kernel.org |
|---|---|
| State | Accepted |
| Commit | 2fa30d0484307dd134a6f923bc8c7d0c89a658f9 |
| Delegated to: | Stefan Roese |
| Headers | show |
| Series | arm: a37xx: pci: Implement workaround for the readback value of VEND_ID | expand |
On 03.03.21 14:37, Pali Rohár wrote: > Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions > document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243): > > The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it > should read 11ABh. > > The firmware can write the correct value, 11ABh, through VEND_ID > (RD0076044h [15:0]). > > Implement this workaround in U-Boot PCIe controller driver aardvark for > both PCI vendor id and PCI subsystem vendor id. > > This change affects PCI vendor id of PCIe root bridge emulated by Linux > kernel. With this change Linux kernel reports correct vendor id 11AB. > > Signed-off-by: Pali Rohár <pali@kernel.org> > --- > drivers/pci/pci-aardvark.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c > index b4e1b602405f..3b9309f52c57 100644 > --- a/drivers/pci/pci-aardvark.c > +++ b/drivers/pci/pci-aardvark.c > @@ -105,6 +105,7 @@ > #define LTSSM_SHIFT 24 > #define LTSSM_MASK 0x3f > #define LTSSM_L0 0x10 > +#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) > > /* PCIe core controller registers */ > #define CTRL_CORE_BASE_ADDR 0x18000 > @@ -529,6 +530,15 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) > reg |= (IS_RC_MSK << IS_RC_SHIFT); > advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); > > + /* > + * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. > + * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor > + * id in high 16 bits. Updating this register changes readback value of > + * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround > + * for erratum 4.1: "The value of device and vendor ID is incorrect". > + */ > + advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG); > + > /* Set Advanced Error Capabilities and Control PF0 register */ > reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | > PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | > Reviewed-by: Stefan Roese <sr@denx.de> Thanks, Stefan
On 03.03.21 14:37, Pali Rohár wrote: > Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions > document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243): > > The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it > should read 11ABh. > > The firmware can write the correct value, 11ABh, through VEND_ID > (RD0076044h [15:0]). > > Implement this workaround in U-Boot PCIe controller driver aardvark for > both PCI vendor id and PCI subsystem vendor id. > > This change affects PCI vendor id of PCIe root bridge emulated by Linux > kernel. With this change Linux kernel reports correct vendor id 11AB. > > Signed-off-by: Pali Rohár <pali@kernel.org> Applied to u-boot-marvell/master Thanks, Stefan > --- > drivers/pci/pci-aardvark.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c > index b4e1b602405f..3b9309f52c57 100644 > --- a/drivers/pci/pci-aardvark.c > +++ b/drivers/pci/pci-aardvark.c > @@ -105,6 +105,7 @@ > #define LTSSM_SHIFT 24 > #define LTSSM_MASK 0x3f > #define LTSSM_L0 0x10 > +#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) > > /* PCIe core controller registers */ > #define CTRL_CORE_BASE_ADDR 0x18000 > @@ -529,6 +530,15 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) > reg |= (IS_RC_MSK << IS_RC_SHIFT); > advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); > > + /* > + * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. > + * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor > + * id in high 16 bits. Updating this register changes readback value of > + * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround > + * for erratum 4.1: "The value of device and vendor ID is incorrect". > + */ > + advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG); > + > /* Set Advanced Error Capabilities and Control PF0 register */ > reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | > PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | > Viele Grüße, Stefan
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index b4e1b602405f..3b9309f52c57 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -105,6 +105,7 @@ #define LTSSM_SHIFT 24 #define LTSSM_MASK 0x3f #define LTSSM_L0 0x10 +#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44) /* PCIe core controller registers */ #define CTRL_CORE_BASE_ADDR 0x18000 @@ -529,6 +530,15 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) reg |= (IS_RC_MSK << IS_RC_SHIFT); advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + /* + * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. + * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor + * id in high 16 bits. Updating this register changes readback value of + * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround + * for erratum 4.1: "The value of device and vendor ID is incorrect". + */ + advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG); + /* Set Advanced Error Capabilities and Control PF0 register */ reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243): The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it should read 11ABh. The firmware can write the correct value, 11ABh, through VEND_ID (RD0076044h [15:0]). Implement this workaround in U-Boot PCIe controller driver aardvark for both PCI vendor id and PCI subsystem vendor id. This change affects PCI vendor id of PCIe root bridge emulated by Linux kernel. With this change Linux kernel reports correct vendor id 11AB. Signed-off-by: Pali Rohár <pali@kernel.org> --- drivers/pci/pci-aardvark.c | 10 ++++++++++ 1 file changed, 10 insertions(+)