diff mbox series

[u-boot-marvell,v2,19/18] ddr: marvell: a38x: Add more space for additional info from SPD

Message ID 20210225050309.26026-1-marek.behun@nic.cz
State Changes Requested
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series Upgrade A38x DDR3 training to version 14.0.0 | expand

Commit Message

Marek Behún Feb. 25, 2021, 5:03 a.m. UTC 
From: "From: Sujeet Baranwal" <sbaranwal@marvell.com>

commit 258be123226f8f5cd516b7813fe201fb7d7416e9 upstream.

At this moment, only page 0 of SPD is being read but to support
smbios, we need to read page 1 also which has more info. In order
to do that, we need to allocate more space.

Signed-off-by: Sujeet Baranwal <sujeet.baranwal@cavium.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Sujeet Kumar Baranwal <Sujeet.Baranwal@cavium.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
---

Stefan, last time I overlooked this commit.
I am sending it as part of series 2, since it can be applied on top of
it.

With the first 18 patches the SPL binary size for turris_omnia_defconfig
rose 36 bytes. With this change it is 424 bytes (which makes sense since
the change is making some structures bigger). It is still okay for all
boards that did not have "SPL too big" problem before this series.

---
 drivers/ddr/marvell/a38x/mv_ddr_spd.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
index b4bfef3103..6043f11b28 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
@@ -40,7 +40,10 @@ 
  */
 union mv_ddr_spd_data {
 	unsigned char all_bytes[MV_DDR_SPD_DATA_BLOCK0_SIZE +
-				MV_DDR_SPD_DATA_BLOCK1M_SIZE];
+				MV_DDR_SPD_DATA_BLOCK1M_SIZE +
+				MV_DDR_SPD_DATA_BLOCK1H_SIZE +
+				MV_DDR_SPD_DATA_BLOCK2E_SIZE +
+				MV_DDR_SPD_DATA_BLOCK2M_SIZE];
 	struct {
 		/* block 0 */
 		union { /* num of bytes used/num of bytes in spd device/crc coverage */
@@ -271,6 +274,9 @@  union mv_ddr_spd_data {
 			} bit_fields;
 		} byte_131;
 		unsigned char bytes_132_191[60]; /* reserved; all 0s */
+		unsigned char bytes_192_255[MV_DDR_SPD_DATA_BLOCK1H_SIZE];
+		unsigned char bytes_256_319[MV_DDR_SPD_DATA_BLOCK2E_SIZE];
+		unsigned char bytes_320_383[MV_DDR_SPD_DATA_BLOCK2M_SIZE];
 	} byte_fields;
 };