| Message ID | 20210224015343.46865-1-elly.siew.chin.lim@intel.com |
|---|---|
| State | Superseded |
| Delegated to: | Simon Goldschmidt |
| Headers | show |
| Series | [v2] Makefile: socfpga: Add target to generate hex output for combined spl and dtb | expand |
> -----Original Message----- > From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com> > Sent: Wednesday, February 24, 2021 9:54 AM > To: u-boot@lists.denx.de > Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon > <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>; > Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin > <elly.siew.chin.lim@intel.com> > Subject: [v2] Makefile: socfpga: Add target to generate hex output for > combined spl and dtb > > From: Dalon Westergreen <dalon.westergreen@intel.com> > > Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel SOCFPGA > SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex" is hex formatted > spl with and offset of CONFIG_SPL_TEXT_BASE. It combines the spl image > and dtb. > "u-boot-spl-dtb.hex" is needed to generate the final configuration bitstream > for Intel SOCFPGA SOC64 devices. > > Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> > > --- > v2: Update commit message > --- > --- > Makefile | 11 ++++++----- > include/configs/socfpga_soc64_common.h | 2 +- > scripts/Makefile.spl | 8 ++++++++ > 3 files changed, 15 insertions(+), 6 deletions(-) > > diff --git a/Makefile b/Makefile > index 4da46dea39..f1adc9aa23 100644 > --- a/Makefile > +++ b/Makefile > @@ -1263,11 +1263,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ > $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ > $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg > -R .resetvec) > > -OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex) > - > -spl/u-boot-spl.hex: spl/u-boot-spl FORCE > - $(call if_changed,objcopy) > - > binary_size_check: u-boot-nodtb.bin FORCE > @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ > map_size=$(shell cat u-boot.map | \ > @@ -1935,6 +1930,12 @@ spl/u-boot-spl.bin: spl/u-boot-spl > @: > $(SPL_SIZE_CHECK) > > +spl/u-boot-spl-dtb.bin: spl/u-boot-spl > + @: > + > +spl/u-boot-spl-dtb.hex: spl/u-boot-spl > + @: > + > spl/u-boot-spl: tools prepare \ > $(if > $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATD > ATA),dts/dt.dtb) \ > $(if > $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATD > ATA),dts/dt.dtb) > diff --git a/include/configs/socfpga_soc64_common.h > b/include/configs/socfpga_soc64_common.h > index fdcd7d3e9a..1af359466c 100644 > --- a/include/configs/socfpga_soc64_common.h > +++ b/include/configs/socfpga_soc64_common.h > @@ -200,7 +200,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); > * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) > * > */ > -#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" > +#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex" > #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE > #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR > #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ > diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index > ea4e045769..625e06d0d9 100644 > --- a/scripts/Makefile.spl > +++ b/scripts/Makefile.spl > @@ -229,6 +229,9 @@ ifneq > ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA > 10),) > INPUTS-y += $(obj)/$(SPL_BIN).sfp > endif > > +INPUTS-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/u-boot-spl- > dtb.hex > +INPUTS-$(CONFIG_TARGET_SOCFPGA_AGILEX) += $(obj)/u- > boot-spl-dtb.hex Can use CONFIG_TARGET_SOCFPGA_SOC64. Regards Ley Foon
Hi Ley Foon, > -----Original Message----- > From: Tan, Ley Foon <ley.foon.tan@intel.com> > Sent: Friday, February 26, 2021 5:38 PM > To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>; u-boot@lists.denx.de > Cc: Marek Vasut <marex@denx.de>; See, Chin Liang > <chin.liang.see@intel.com>; Simon Goldschmidt > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > Yau Wai <yau.wai.gan@intel.com> > Subject: RE: [v2] Makefile: socfpga: Add target to generate hex output for > combined spl and dtb > > > > > -----Original Message----- > > From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com> > > Sent: Wednesday, February 24, 2021 9:54 AM > > To: u-boot@lists.denx.de > > Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon > > <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>; > > Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > > <tien.fong.chee@intel.com>; Westergreen, Dalon > > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > > Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin > > <elly.siew.chin.lim@intel.com> > > Subject: [v2] Makefile: socfpga: Add target to generate hex output for > > combined spl and dtb > > > > From: Dalon Westergreen <dalon.westergreen@intel.com> > > > > Add target to Makefile to generate "u-boot-spl-dtb.hex" for Intel > > SOCFPGA > > SOC64 devices (Stratix 10 and Agilex). "u-boot-spl-dtb.hex" is hex > > formatted spl with and offset of CONFIG_SPL_TEXT_BASE. It combines the > > spl image and dtb. > > "u-boot-spl-dtb.hex" is needed to generate the final configuration > > bitstream for Intel SOCFPGA SOC64 devices. > > > > Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> > > > > --- > > v2: Update commit message > > --- > > --- > > Makefile | 11 ++++++----- > > include/configs/socfpga_soc64_common.h | 2 +- > > scripts/Makefile.spl | 8 ++++++++ > > 3 files changed, 15 insertions(+), 6 deletions(-) > > > > diff --git a/Makefile b/Makefile > > index 4da46dea39..f1adc9aa23 100644 > > --- a/Makefile > > +++ b/Makefile > > @@ -1263,11 +1263,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ > > $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ > > $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg > -R .resetvec) > > > > -OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex) > > - > > -spl/u-boot-spl.hex: spl/u-boot-spl FORCE > > - $(call if_changed,objcopy) > > - > > binary_size_check: u-boot-nodtb.bin FORCE > > @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ > > map_size=$(shell cat u-boot.map | \ > > @@ -1935,6 +1930,12 @@ spl/u-boot-spl.bin: spl/u-boot-spl > > @: > > $(SPL_SIZE_CHECK) > > > > +spl/u-boot-spl-dtb.bin: spl/u-boot-spl > > + @: > > + > > +spl/u-boot-spl-dtb.hex: spl/u-boot-spl > > + @: > > + > > spl/u-boot-spl: tools prepare \ > > $(if > > > $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATD > > ATA),dts/dt.dtb) \ > > $(if > > > $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATD > > ATA),dts/dt.dtb) > > diff --git a/include/configs/socfpga_soc64_common.h > > b/include/configs/socfpga_soc64_common.h > > index fdcd7d3e9a..1af359466c 100644 > > --- a/include/configs/socfpga_soc64_common.h > > +++ b/include/configs/socfpga_soc64_common.h > > @@ -200,7 +200,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); > > * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) > > * > > */ > > -#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" > > +#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex" > > #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE > > #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR > > #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 > MB */ > > diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index > > ea4e045769..625e06d0d9 100644 > > --- a/scripts/Makefile.spl > > +++ b/scripts/Makefile.spl > > @@ -229,6 +229,9 @@ ifneq > > > ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA > > 10),) > > INPUTS-y += $(obj)/$(SPL_BIN).sfp > > endif > > > > +INPUTS-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/u-boot-spl- > > dtb.hex > > +INPUTS-$(CONFIG_TARGET_SOCFPGA_AGILEX) += $(obj)/u- > > boot-spl-dtb.hex > > Can use CONFIG_TARGET_SOCFPGA_SOC64. I have changed to use TARGET_SOCFPGA_SOC64. I have included this patch in 4th version of VAB series because it is depending on TARGET_SOCFPGA_SOC64 patch in VAB series. Thanks. > > Regards > Ley Foon
diff --git a/Makefile b/Makefile index 4da46dea39..f1adc9aa23 100644 --- a/Makefile +++ b/Makefile @@ -1263,11 +1263,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec) -OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex) - -spl/u-boot-spl.hex: spl/u-boot-spl FORCE - $(call if_changed,objcopy) - binary_size_check: u-boot-nodtb.bin FORCE @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ map_size=$(shell cat u-boot.map | \ @@ -1935,6 +1930,12 @@ spl/u-boot-spl.bin: spl/u-boot-spl @: $(SPL_SIZE_CHECK) +spl/u-boot-spl-dtb.bin: spl/u-boot-spl + @: + +spl/u-boot-spl-dtb.hex: spl/u-boot-spl + @: + spl/u-boot-spl: tools prepare \ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index fdcd7d3e9a..1af359466c 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -200,7 +200,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) * */ -#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" +#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex" #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index ea4e045769..625e06d0d9 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -229,6 +229,9 @@ ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) INPUTS-y += $(obj)/$(SPL_BIN).sfp endif +INPUTS-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/u-boot-spl-dtb.hex +INPUTS-$(CONFIG_TARGET_SOCFPGA_AGILEX) += $(obj)/u-boot-spl-dtb.hex + ifdef CONFIG_ARCH_SUNXI INPUTS-y += $(obj)/sunxi-spl.bin @@ -389,6 +392,11 @@ $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \ -n $(CONFIG_DEFAULT_DEVICE_TREE) +OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) + +$(obj)/u-boot-spl-dtb.hex: $(obj)/u-boot-spl-dtb.bin FORCE + $(call if_changed,objcopy) + $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE $(call if_changed,mkimage)