diff mbox series

[47/57] ppc: Remove gdsys hrcon boards

Message ID 20210221010634.21310-48-trini@konsulko.com
State Accepted
Commit 7c964c3b93671dbc27eebc876ec592db7ac88ec6
Delegated to: Tom Rini
Headers show
Series Enforce DM_MMC migration and remove platforms | expand

Commit Message

Tom Rini Feb. 21, 2021, 1:06 a.m. UTC
These boards have not been converted to CONFIG_DM_MMC, along with other
DM conversions, by the deadline.  Remove them.

Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/powerpc/cpu/mpc83xx/Kconfig |   4 -
 board/gdsys/common/Makefile      |   1 -
 board/gdsys/common/fanctrl.c     |  35 ---
 board/gdsys/common/fanctrl.h     |  12 -
 board/gdsys/common/mclink.c      | 141 ---------
 board/gdsys/common/mclink.h      |  14 -
 board/gdsys/common/phy.c         | 278 -----------------
 board/gdsys/common/phy.h         |  13 -
 board/gdsys/mpc8308/Kconfig      |  26 +-
 board/gdsys/mpc8308/MAINTAINERS  |   4 +-
 board/gdsys/mpc8308/Makefile     |   1 -
 board/gdsys/mpc8308/hrcon.c      | 504 -------------------------------
 configs/hrcon_defconfig          | 147 ---------
 configs/hrcon_dh_defconfig       | 145 ---------
 include/configs/hrcon.h          | 421 --------------------------
 include/gdsys_fpga.h             |  46 ---
 16 files changed, 3 insertions(+), 1789 deletions(-)
 delete mode 100644 board/gdsys/common/fanctrl.c
 delete mode 100644 board/gdsys/common/fanctrl.h
 delete mode 100644 board/gdsys/common/mclink.c
 delete mode 100644 board/gdsys/common/mclink.h
 delete mode 100644 board/gdsys/common/phy.c
 delete mode 100644 board/gdsys/common/phy.h
 delete mode 100644 board/gdsys/mpc8308/hrcon.c
 delete mode 100644 configs/hrcon_defconfig
 delete mode 100644 configs/hrcon_dh_defconfig
 delete mode 100644 include/configs/hrcon.h

Comments

Tom Rini April 12, 2021, 12:28 a.m. UTC | #1
On Sat, Feb 20, 2021 at 08:06:24PM -0500, Tom Rini wrote:

> These boards have not been converted to CONFIG_DM_MMC, along with other
> DM conversions, by the deadline.  Remove them.
> 
> Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
> Signed-off-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 3ca56695af89..d2c620e22954 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -137,10 +137,6 @@  config TARGET_TQM834X
 	bool "Support TQM834x"
 	select ARCH_MPC8349
 
-config TARGET_HRCON
-	bool "Support hrcon"
-	select ARCH_MPC8308
-	select SYS_FSL_ERRATUM_ESDHC111
 
 config TARGET_GAZERBEAM
 	bool "Support gazerbeam"
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index fa4c65c63478..dd6d5e69de56 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -6,7 +6,6 @@ 
 obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
 obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
 obj-$(CONFIG_CONTROLCENTERD) += dp501.o
-obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
 obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o
 
 ifdef CONFIG_OSD
diff --git a/board/gdsys/common/fanctrl.c b/board/gdsys/common/fanctrl.c
deleted file mode 100644
index 27c875cbec07..000000000000
--- a/board/gdsys/common/fanctrl.c
+++ /dev/null
@@ -1,35 +0,0 @@ 
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
-
-#include <common.h>
-#include <i2c.h>
-
-enum {
-	FAN_CONFIG = 0x03,
-	FAN_TACHLIM_LSB = 0x48,
-	FAN_TACHLIM_MSB = 0x49,
-	FAN_PWM_FREQ = 0x4D,
-};
-
-void init_fan_controller(u8 addr)
-{
-	int val;
-
-	/* set PWM Frequency to 2.5% resolution */
-	i2c_reg_write(addr, FAN_PWM_FREQ, 20);
-
-	/* set Tachometer Limit */
-	i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10);
-	i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a);
-
-	/* enable Tach input */
-	val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
-	i2c_reg_write(addr, FAN_CONFIG, val);
-}
-
-#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/fanctrl.h b/board/gdsys/common/fanctrl.h
deleted file mode 100644
index ab7e58def5a0..000000000000
--- a/board/gdsys/common/fanctrl.h
+++ /dev/null
@@ -1,12 +0,0 @@ 
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#ifndef _FANCTRL_H_
-#define _FANCTRL_H_
-
-void init_fan_controller(u8 addr);
-
-#endif
diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c
deleted file mode 100644
index 6147fbfc87fb..000000000000
--- a/board/gdsys/common/mclink.c
+++ /dev/null
@@ -1,141 +0,0 @@ 
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2012
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
-
-#include <common.h>
-#include <asm/io.h>
-#include <errno.h>
-
-#include <gdsys_fpga.h>
-#include <linux/delay.h>
-
-enum {
-	MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7,
-	MCINT_TX_ERROR_EV = 1 << 9,
-	MCINT_TX_BUFFER_FREE = 1 << 10,
-	MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11,
-	MCINT_RX_ERROR_EV = 1 << 13,
-	MCINT_RX_CONTENT_AVAILABLE = 1 << 14,
-	MCINT_RX_PACKET_RECEIVED_EV = 1 << 15,
-};
-
-int mclink_probe(void)
-{
-	unsigned int k;
-	int slaves = 0;
-
-	for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) {
-		int timeout = 0;
-		unsigned int ctr = 0;
-		u16 mc_status;
-
-		FPGA_GET_REG(k, mc_status, &mc_status);
-
-		if (!(mc_status & (1 << 15)))
-			break;
-
-		FPGA_SET_REG(k, mc_control, 0x8000);
-
-		FPGA_GET_REG(k, mc_status, &mc_status);
-		while (!(mc_status & (1 << 14))) {
-			udelay(100);
-			if (ctr++ > 500) {
-				timeout = 1;
-				break;
-			}
-			FPGA_GET_REG(k, mc_status, &mc_status);
-		}
-		if (timeout)
-			break;
-
-		printf("waited %d us for mclink %d to come up\n", ctr * 100, k);
-
-		slaves++;
-	}
-
-	return slaves;
-}
-
-int mclink_send(u8 slave, u16 addr, u16 data)
-{
-	unsigned int ctr = 0;
-	u16 int_status;
-	u16 rx_cmd_status;
-	u16 rx_cmd;
-
-	/* reset interrupt status */
-	FPGA_GET_REG(0, mc_int, &int_status);
-	FPGA_SET_REG(0, mc_int, int_status);
-
-	/* send */
-	FPGA_SET_REG(0, mc_tx_address, addr);
-	FPGA_SET_REG(0, mc_tx_data, data);
-	FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14);
-	FPGA_SET_REG(0, mc_control, 0x8001);
-
-	/* wait for reply */
-	FPGA_GET_REG(0, mc_int, &int_status);
-	while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) {
-		udelay(100);
-		if (ctr++ > 3)
-			return -ETIMEDOUT;
-		FPGA_GET_REG(0, mc_int, &int_status);
-	}
-
-	FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
-	rx_cmd = (rx_cmd_status >> 12) & 0x03;
-	if (rx_cmd != 0)
-		printf("mclink_send: received cmd %d, expected %d\n", rx_cmd,
-		       0);
-
-	return 0;
-}
-
-int mclink_receive(u8 slave, u16 addr, u16 *data)
-{
-	u16 rx_cmd_status;
-	u16 rx_cmd;
-	u16 int_status;
-	unsigned int ctr = 0;
-
-	/* send read request */
-	FPGA_SET_REG(0, mc_tx_address, addr);
-	FPGA_SET_REG(0, mc_tx_cmd,
-		     ((slave & 0x03) << 14) | (1 << 12) | (1 << 0));
-	FPGA_SET_REG(0, mc_control, 0x8001);
-
-
-	/* wait for reply */
-	FPGA_GET_REG(0, mc_int, &int_status);
-	while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) {
-		udelay(100);
-		if (ctr++ > 3)
-			return -ETIMEDOUT;
-		FPGA_GET_REG(0, mc_int, &int_status);
-	}
-
-	/* check reply */
-	FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
-	if ((rx_cmd_status >> 14) != slave) {
-		printf("mclink_receive: reply from slave %d, expected %d\n",
-		       rx_cmd_status >> 14, slave);
-		return -EINVAL;
-	}
-
-	rx_cmd = (rx_cmd_status >> 12) & 0x03;
-	if (rx_cmd != 1) {
-		printf("mclink_send: received cmd %d, expected %d\n",
-		       rx_cmd, 1);
-		return -EIO;
-	}
-
-	FPGA_GET_REG(0, mc_rx_data, data);
-
-	return 0;
-}
-
-#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
diff --git a/board/gdsys/common/mclink.h b/board/gdsys/common/mclink.h
deleted file mode 100644
index 4dc405889243..000000000000
--- a/board/gdsys/common/mclink.h
+++ /dev/null
@@ -1,14 +0,0 @@ 
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2012
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#ifndef _MCLINK_H_
-#define _MCLINK_H_
-
-int mclink_probe(void);
-int mclink_send(u8 slave, u16 addr, u16 data);
-int mclink_receive(u8 slave, u16 addr, u16 *data);
-
-#endif
diff --git a/board/gdsys/common/phy.c b/board/gdsys/common/phy.c
deleted file mode 100644
index 516f4e8edcac..000000000000
--- a/board/gdsys/common/phy.c
+++ /dev/null
@@ -1,278 +0,0 @@ 
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#include <common.h>
-#include <log.h>
-
-#include <miiphy.h>
-
-enum {
-	MIICMD_SET,
-	MIICMD_MODIFY,
-	MIICMD_VERIFY_VALUE,
-	MIICMD_WAIT_FOR_VALUE,
-};
-
-struct mii_setupcmd {
-	u8 token;
-	u8 reg;
-	u16 data;
-	u16 mask;
-	u32 timeout;
-};
-
-/*
- * verify we are talking to a 88e1518
- */
-struct mii_setupcmd verify_88e1518[] = {
-	{ MIICMD_SET, 22, 0x0000 },
-	{ MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff },
-	{ MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
-};
-
-/*
- * workaround for erratum mentioned in 88E1518 release notes
- */
-struct mii_setupcmd fixup_88e1518[] = {
-	{ MIICMD_SET, 22, 0x00ff },
-	{ MIICMD_SET, 17, 0x214b },
-	{ MIICMD_SET, 16, 0x2144 },
-	{ MIICMD_SET, 17, 0x0c28 },
-	{ MIICMD_SET, 16, 0x2146 },
-	{ MIICMD_SET, 17, 0xb233 },
-	{ MIICMD_SET, 16, 0x214d },
-	{ MIICMD_SET, 17, 0xcc0c },
-	{ MIICMD_SET, 16, 0x2159 },
-	{ MIICMD_SET, 22, 0x0000 },
-};
-
-/*
- * default initialization:
- * - set RGMII receive timing to "receive clock transition when data stable"
- * - set RGMII transmit timing to "transmit clock internally delayed"
- * - set RGMII output impedance target to 78,8 Ohm
- * - run output impedance calibration
- * - set autonegotiation advertise to 1000FD only
- */
-struct mii_setupcmd default_88e1518[] = {
-	{ MIICMD_SET, 22, 0x0002 },
-	{ MIICMD_MODIFY, 21, 0x0030, 0x0030 },
-	{ MIICMD_MODIFY, 25, 0x0000, 0x0003 },
-	{ MIICMD_MODIFY, 24, 0x8000, 0x8000 },
-	{ MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 },
-	{ MIICMD_SET, 22, 0x0000 },
-	{ MIICMD_MODIFY, 4, 0x0000, 0x01e0 },
-	{ MIICMD_MODIFY, 9, 0x0200, 0x0300 },
-};
-
-/*
- * turn off CLK125 for PHY daughterboard
- */
-struct mii_setupcmd ch1fix_88e1518[] = {
-	{ MIICMD_SET, 22, 0x0002 },
-	{ MIICMD_MODIFY, 16, 0x0006, 0x0006 },
-	{ MIICMD_SET, 22, 0x0000 },
-};
-
-/*
- * perform copper software reset
- */
-struct mii_setupcmd swreset_88e1518[] = {
-	{ MIICMD_SET, 22, 0x0000 },
-	{ MIICMD_MODIFY, 0, 0x8000, 0x8000 },
-	{ MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 },
-};
-
-/*
- * special one for 88E1514:
- * Force SGMII to Copper mode
- */
-struct mii_setupcmd mii_to_copper_88e1514[] = {
-	{ MIICMD_SET, 22, 0x0012 },
-	{ MIICMD_MODIFY, 20, 0x0001, 0x0007 },
-	{ MIICMD_MODIFY, 20, 0x8000, 0x8000 },
-	{ MIICMD_SET, 22, 0x0000 },
-};
-
-/*
- * turn off SGMII auto-negotiation
- */
-struct mii_setupcmd sgmii_autoneg_off_88e1518[] = {
-	{ MIICMD_SET, 22, 0x0001 },
-	{ MIICMD_MODIFY, 0, 0x0000, 0x1000 },
-	{ MIICMD_MODIFY, 0, 0x8000, 0x8000 },
-	{ MIICMD_SET, 22, 0x0000 },
-};
-
-/*
- * invert LED2 polarity
- */
-struct mii_setupcmd invert_led2_88e1514[] = {
-	{ MIICMD_SET, 22, 0x0003 },
-	{ MIICMD_MODIFY, 17, 0x0030, 0x0010 },
-	{ MIICMD_SET, 22, 0x0000 },
-};
-
-static int process_setupcmd(const char *bus, unsigned char addr,
-			    struct mii_setupcmd *setupcmd)
-{
-	int res;
-	u8 reg = setupcmd->reg;
-	u16 data = setupcmd->data;
-	u16 mask = setupcmd->mask;
-	u32 timeout = setupcmd->timeout;
-	u16 orig_data;
-	unsigned long start;
-
-	debug("mii %s:%u reg %2u ", bus, addr, reg);
-
-	switch (setupcmd->token) {
-	case MIICMD_MODIFY:
-		res = miiphy_read(bus, addr, reg, &orig_data);
-		if (res)
-			break;
-		debug("is %04x. (value %04x mask %04x) ", orig_data, data,
-		      mask);
-		data = (orig_data & ~mask) | (data & mask);
-		/* fallthrough */
-	case MIICMD_SET:
-		debug("=> %04x\n", data);
-		res = miiphy_write(bus, addr, reg, data);
-		break;
-	case MIICMD_VERIFY_VALUE:
-		res = miiphy_read(bus, addr, reg, &orig_data);
-		if (res)
-			break;
-		if ((orig_data & mask) != (data & mask))
-			res = -1;
-		debug("(value %04x mask %04x) == %04x? %s\n", data, mask,
-		      orig_data, res ? "FAIL" : "PASS");
-		break;
-	case MIICMD_WAIT_FOR_VALUE:
-		res = -1;
-		start = get_timer(0);
-		while ((res != 0) && (get_timer(start) < timeout)) {
-			res = miiphy_read(bus, addr, reg, &orig_data);
-			if (res)
-				continue;
-			if ((orig_data & mask) != (data & mask))
-				res = -1;
-		}
-		debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data,
-		      mask, orig_data, res ? "FAIL" : "PASS",
-		      get_timer(start));
-		break;
-	default:
-		res = -1;
-		break;
-	}
-
-	return res;
-}
-
-static int process_setup(const char *bus, unsigned char addr,
-			    struct mii_setupcmd *setupcmd, unsigned int count)
-{
-	int res = 0;
-	unsigned int k;
-
-	for (k = 0; k < count; ++k) {
-		res = process_setupcmd(bus, addr, &setupcmd[k]);
-		if (res) {
-			printf("mii cmd %u on bus %s addr %u failed, aborting setup\n",
-			       setupcmd[k].token, bus, addr);
-			break;
-		}
-	}
-
-	return res;
-}
-
-int setup_88e1518(const char *bus, unsigned char addr)
-{
-	int res;
-
-	res = process_setup(bus, addr,
-			    verify_88e1518, ARRAY_SIZE(verify_88e1518));
-	if (res)
-		return res;
-
-	res = process_setup(bus, addr,
-			    fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
-	if (res)
-		return res;
-
-	res = process_setup(bus, addr,
-			    default_88e1518, ARRAY_SIZE(default_88e1518));
-	if (res)
-		return res;
-
-	if (addr) {
-		res = process_setup(bus, addr,
-				    ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
-		if (res)
-			return res;
-	}
-
-	res = process_setup(bus, addr,
-			    swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
-	if (res)
-		return res;
-
-	return 0;
-}
-
-int setup_88e1514(const char *bus, unsigned char addr)
-{
-	int res;
-
-	res = process_setup(bus, addr,
-			    verify_88e1518, ARRAY_SIZE(verify_88e1518));
-	if (res)
-		return res;
-
-	res = process_setup(bus, addr,
-			    fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
-	if (res)
-		return res;
-
-	res = process_setup(bus, addr,
-			    mii_to_copper_88e1514,
-			    ARRAY_SIZE(mii_to_copper_88e1514));
-	if (res)
-		return res;
-
-	res = process_setup(bus, addr,
-			    sgmii_autoneg_off_88e1518,
-			    ARRAY_SIZE(sgmii_autoneg_off_88e1518));
-	if (res)
-		return res;
-
-	res = process_setup(bus, addr,
-			    invert_led2_88e1514,
-			    ARRAY_SIZE(invert_led2_88e1514));
-	if (res)
-		return res;
-
-	res = process_setup(bus, addr,
-			    default_88e1518, ARRAY_SIZE(default_88e1518));
-	if (res)
-		return res;
-
-	if (addr) {
-		res = process_setup(bus, addr,
-				    ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
-		if (res)
-			return res;
-	}
-
-	res = process_setup(bus, addr,
-			    swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
-	if (res)
-		return res;
-
-	return 0;
-}
diff --git a/board/gdsys/common/phy.h b/board/gdsys/common/phy.h
deleted file mode 100644
index e0aa661b9c49..000000000000
--- a/board/gdsys/common/phy.h
+++ /dev/null
@@ -1,13 +0,0 @@ 
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#ifndef _PHY_H_
-#define _PHY_H_
-
-int setup_88e1514(const char *bus, unsigned char addr);
-int setup_88e1518(const char *bus, unsigned char addr);
-
-#endif
diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig
index 1c33f0c982d2..c3fd0518bc4c 100644
--- a/board/gdsys/mpc8308/Kconfig
+++ b/board/gdsys/mpc8308/Kconfig
@@ -1,3 +1,5 @@ 
+if TARGET_GAZERBEAM
+
 config GDSYS_LEGACY_OSD_CMDS
 	bool
 	help
@@ -33,27 +35,6 @@  config SYS_FPGA1_SIZE
 	help
 	  The base address of the second FPGA's register map.
 
-if TARGET_HRCON
-
-config SYS_BOARD
-	default "mpc8308"
-
-config SYS_VENDOR
-	default "gdsys"
-
-config SYS_CONFIG_NAME
-	default "hrcon"
-
-config GDSYS_LEGACY_OSD_CMDS
-	default y
-
-config GDSYS_LEGACY_DRIVERS
-	default y
-
-endif
-
-if TARGET_GAZERBEAM
-
 config SYS_BOARD
 	default "mpc8308"
 
@@ -71,9 +52,6 @@  config SYS_FPGA1_SIZE
 
 config GDSYS_LEGACY_OSD_CMDS
 	default y
-endif
-
-if TARGET_HRCON || TARGET_GAZERBEAM
 
 choice
 	prompt "FPGA flavor selection"
diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS
index cc0fbebccd41..dc0b389f73c2 100644
--- a/board/gdsys/mpc8308/MAINTAINERS
+++ b/board/gdsys/mpc8308/MAINTAINERS
@@ -2,7 +2,5 @@  MPC8308 BOARD
 M:	Dirk Eibach <dirk.eibach@gdsys.cc>
 S:	Maintained
 F:	board/gdsys/mpc8308/
-F:	include/configs/hrcon.h
-F:	configs/hrcon_defconfig
-F:	configs/hrcon_dh_defconfig
+F:	include/configs/gazerbeam.h
 F:	configs/gazerbeam_defconfig
diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile
index 578b36653d82..f86d997bc79c 100644
--- a/board/gdsys/mpc8308/Makefile
+++ b/board/gdsys/mpc8308/Makefile
@@ -4,5 +4,4 @@ 
 # Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
 
 obj-y := mpc8308.o sdram.o
-obj-$(CONFIG_TARGET_HRCON) += hrcon.o
 obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o
diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c
deleted file mode 100644
index b5c681c2d1eb..000000000000
--- a/board/gdsys/mpc8308/hrcon.c
+++ /dev/null
@@ -1,504 +0,0 @@ 
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- */
-
-#include <common.h>
-#include <env.h>
-#include <flash.h>
-#include <hwconfig.h>
-#include <i2c.h>
-#include <init.h>
-#include <spi.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <fsl_esdhc.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_mpc83xx_serdes.h>
-
-#include "mpc8308.h"
-
-#include <gdsys_fpga.h>
-
-#include "../common/ioep-fpga.h"
-#include "../common/osd.h"
-#include "../common/mclink.h"
-#include "../common/phy.h"
-#include "../common/fanctrl.h"
-
-#include <pca953x.h>
-#include <pca9698.h>
-
-#include <miiphy.h>
-
-#define MAX_MUX_CHANNELS 2
-
-enum {
-	MCFPGA_DONE = BIT(0),
-	MCFPGA_INIT_N = BIT(1),
-	MCFPGA_PROGRAM_N = BIT(2),
-	MCFPGA_UPDATE_ENABLE_N = BIT(3),
-	MCFPGA_RESET_N = BIT(4),
-};
-
-enum {
-	GPIO_MDC = 1 << 14,
-	GPIO_MDIO = 1 << 15,
-};
-
-uint mclink_fpgacount;
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-struct {
-	u8 bus;
-	u8 addr;
-} hrcon_fans[] = CONFIG_HRCON_FANS;
-
-int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
-{
-	int res;
-
-	switch (fpga) {
-	case 0:
-		out_le16(reg, data);
-		break;
-	default:
-		res = mclink_send(fpga - 1, regoff, data);
-		if (res < 0) {
-			printf("mclink_send reg %02lx data %04x returned %d\n",
-			       regoff, data, res);
-			return res;
-		}
-		break;
-	}
-
-	return 0;
-}
-
-int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
-{
-	int res;
-
-	switch (fpga) {
-	case 0:
-		*data = in_le16(reg);
-		break;
-	default:
-		if (fpga > mclink_fpgacount)
-			return -EINVAL;
-		res = mclink_receive(fpga - 1, regoff, data);
-		if (res < 0) {
-			printf("mclink_receive reg %02lx returned %d\n",
-			       regoff, res);
-			return res;
-		}
-	}
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char *s = env_get("serial#");
-	bool hw_type_cat = pca9698_get_value(0x20, 20);
-
-	puts("Board: ");
-
-	printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
-
-	if (s) {
-		puts(", serial# ");
-		puts(s);
-	}
-
-	puts("\n");
-
-	return 0;
-}
-
-int last_stage_init(void)
-{
-	int slaves;
-	uint k;
-	uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
-	u16 fpga_features;
-	bool hw_type_cat = pca9698_get_value(0x20, 20);
-	bool ch0_rgmii2_present;
-
-	FPGA_GET_REG(0, fpga_features, &fpga_features);
-
-	/* Turn on Parade DP501 */
-	pca9698_direction_output(0x20, 10, 1);
-	pca9698_direction_output(0x20, 11, 1);
-
-	ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
-
-	/* wait for FPGA done, then reset FPGA */
-	for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
-		uint ctr = 0;
-
-		if (i2c_probe(mclink_controllers[k]))
-			continue;
-
-		while (!(pca953x_get_val(mclink_controllers[k])
-		       & MCFPGA_DONE)) {
-			mdelay(100);
-			if (ctr++ > 5) {
-				printf("no done for mclink_controller %u\n", k);
-				break;
-			}
-		}
-
-		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
-		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
-		udelay(10);
-		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
-				MCFPGA_RESET_N);
-	}
-
-	if (hw_type_cat) {
-		uint mux_ch;
-		int retval;
-		struct mii_dev *mdiodev = mdio_alloc();
-
-		if (!mdiodev)
-			return -ENOMEM;
-		strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
-		mdiodev->read = bb_miiphy_read;
-		mdiodev->write = bb_miiphy_write;
-
-		retval = mdio_register(mdiodev);
-		if (retval < 0)
-			return retval;
-		for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
-			if ((mux_ch == 1) && !ch0_rgmii2_present)
-				continue;
-
-			setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
-		}
-	}
-
-	/* give slave-PLLs and Parade DP501 some time to be up and running */
-	mdelay(500);
-
-	mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
-	slaves = mclink_probe();
-	mclink_fpgacount = 0;
-
-	ioep_fpga_print_info(0);
-	osd_probe(0);
-#ifdef CONFIG_SYS_OSD_DH
-	osd_probe(4);
-#endif
-
-	if (slaves <= 0)
-		return 0;
-
-	mclink_fpgacount = slaves;
-
-	for (k = 1; k <= slaves; ++k) {
-		FPGA_GET_REG(k, fpga_features, &fpga_features);
-
-		ioep_fpga_print_info(k);
-		osd_probe(k);
-#ifdef CONFIG_SYS_OSD_DH
-		osd_probe(k + 4);
-#endif
-		if (hw_type_cat) {
-			int retval;
-			struct mii_dev *mdiodev = mdio_alloc();
-
-			if (!mdiodev)
-				return -ENOMEM;
-			strncpy(mdiodev->name, bb_miiphy_buses[k].name,
-				MDIO_NAME_LEN);
-			mdiodev->read = bb_miiphy_read;
-			mdiodev->write = bb_miiphy_write;
-
-			retval = mdio_register(mdiodev);
-			if (retval < 0)
-				return retval;
-			setup_88e1514(bb_miiphy_buses[k].name, 0);
-		}
-	}
-
-	for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
-		i2c_set_bus_num(hrcon_fans[k].bus);
-		init_fan_controller(hrcon_fans[k].addr);
-	}
-
-	return 0;
-}
-
-/*
- * provide access to fpga gpios and controls (for I2C bitbang)
- * (these may look all too simple but make iocon.h much more readable)
- */
-void fpga_gpio_set(uint bus, int pin)
-{
-	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
-}
-
-void fpga_gpio_clear(uint bus, int pin)
-{
-	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
-}
-
-int fpga_gpio_get(uint bus, int pin)
-{
-	u16 val;
-
-	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
-
-	return val & pin;
-}
-
-void fpga_control_set(uint bus, int pin)
-{
-	u16 val;
-
-	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
-	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
-}
-
-void fpga_control_clear(uint bus, int pin)
-{
-	u16 val;
-
-	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
-	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
-}
-
-void mpc8308_init(void)
-{
-	pca9698_direction_output(0x20, 4, 1);
-}
-
-void mpc8308_set_fpga_reset(uint state)
-{
-	pca9698_set_value(0x20, 4, state ? 0 : 1);
-}
-
-void mpc8308_setup_hw(void)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
-	/*
-	 * set "startup-finished"-gpios
-	 */
-	setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
-	setbits_gpio0_out(BIT(31 - 12));
-}
-
-int mpc8308_get_fpga_done(uint fpga)
-{
-	return pca9698_get_value(0x20, 19);
-}
-
-#ifdef CONFIG_FSL_ESDHC
-int board_mmc_init(struct bd_info *bd)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	sysconf83xx_t *sysconf = &immr->sysconf;
-
-	/* Enable cache snooping in eSDHC system configuration register */
-	out_be32(&sysconf->sdhccr, 0x02000000);
-
-	return fsl_esdhc_mmc_init(bd);
-}
-#endif
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	sysconf83xx_t *sysconf = &immr->sysconf;
-	law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *pcie_reg[] = { pcie_regions_0 };
-
-	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
-			 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(1, pcie_reg);
-}
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
-	info->portwidth = FLASH_CFI_16BIT;
-	info->chipwidth = FLASH_CFI_BY16;
-	info->interface = FLASH_CFI_X16;
-	return 1;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-	fsl_fdt_fixup_dr_usb(blob, bd);
-	fdt_fixup_esdhc(blob, bd);
-
-	return 0;
-}
-#endif
-
-/*
- * FPGA MII bitbang implementation
- */
-
-struct fpga_mii {
-	uint fpga;
-	int mdio;
-} fpga_mii[] = {
-	{ 0, 1},
-	{ 1, 1},
-	{ 2, 1},
-	{ 3, 1},
-};
-
-static int mii_dummy_init(struct bb_miiphy_bus *bus)
-{
-	return 0;
-}
-
-static int mii_mdio_active(struct bb_miiphy_bus *bus)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	if (fpga_mii->mdio)
-		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
-	else
-		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
-
-	return 0;
-}
-
-static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
-
-	return 0;
-}
-
-static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	if (v)
-		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
-	else
-		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
-
-	fpga_mii->mdio = v;
-
-	return 0;
-}
-
-static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
-	u16 gpio;
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
-
-	*v = ((gpio & GPIO_MDIO) != 0);
-
-	return 0;
-}
-
-static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	if (v)
-		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
-	else
-		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
-
-	return 0;
-}
-
-static int mii_delay(struct bb_miiphy_bus *bus)
-{
-	udelay(1);
-
-	return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
-	{
-		.name = "board0",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[0],
-	},
-	{
-		.name = "board1",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[1],
-	},
-	{
-		.name = "board2",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[2],
-	},
-	{
-		.name = "board3",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[3],
-	},
-};
-
-int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
deleted file mode 100644
index 5ac6de62ae36..000000000000
--- a/configs/hrcon_defconfig
+++ /dev/null
@@ -1,147 +0,0 @@ 
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_IDENT_STRING=" hrcon 0.01"
-CONFIG_SYS_CLK_FREQ=33333333
-CONFIG_MPC83xx=y
-CONFIG_TARGET_HRCON=y
-CONFIG_SYSTEM_PLL_VCO_DIV_2=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_3_1=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_RGMII=y
-CONFIG_TSEC2_MODE_RGMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="DDR"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_128_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMRBAR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_8_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="FLASH"
-CONFIG_BAT2_BASE=0xFE000000
-CONFIG_BAT2_LENGTH_8_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="STACK_IN_DCACHE"
-CONFIG_BAT3_BASE=0xE6000000
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE0600000
-CONFIG_LBLAW1_NAME="FPGA0"
-CONFIG_LBLAW1_LENGTH_1_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FPGA"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_1_MBYTES=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_DPM=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
-CONFIG_SICR_IEEE1588_A_GPIO=y
-CONFIG_SICR_GTM_GPIO=y
-CONFIG_SICR_ETSEC2_GPIO=y
-CONFIG_SICR_GPIOSEL_IEEE1588=y
-CONFIG_SICR_TMSOBI1_2_5_V=y
-CONFIG_SICR_TMSOBI2_2_5_V=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSECEP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_CMD_IOLOOP=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=5
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_USE_PREBOOT=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_FPGAD=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFE060000
-CONFIG_ENV_ADDR_REDUND=0xFE070000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_BITBANGMII=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
deleted file mode 100644
index ca938940e9d6..000000000000
--- a/configs/hrcon_dh_defconfig
+++ /dev/null
@@ -1,145 +0,0 @@ 
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFE000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_IDENT_STRING=" hrcon dh 0.01"
-CONFIG_SYS_CLK_FREQ=33333333
-CONFIG_MPC83xx=y
-CONFIG_TARGET_HRCON=y
-CONFIG_SYSTEM_PLL_VCO_DIV_2=y
-CONFIG_SYSTEM_PLL_FACTOR_4_1=y
-CONFIG_CORE_PLL_RATIO_3_1=y
-CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
-CONFIG_TSEC1_MODE_RGMII=y
-CONFIG_TSEC2_MODE_RGMII=y
-CONFIG_BAT0=y
-CONFIG_BAT0_NAME="DDR"
-CONFIG_BAT0_BASE=0x00000000
-CONFIG_BAT0_LENGTH_128_MBYTES=y
-CONFIG_BAT0_ACCESS_RW=y
-CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
-CONFIG_BAT0_USER_MODE_VALID=y
-CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT1=y
-CONFIG_BAT1_NAME="IMMRBAR"
-CONFIG_BAT1_BASE=0xE0000000
-CONFIG_BAT1_LENGTH_8_MBYTES=y
-CONFIG_BAT1_ACCESS_RW=y
-CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
-CONFIG_BAT1_DCACHE_INHIBITED=y
-CONFIG_BAT1_DCACHE_GUARDED=y
-CONFIG_BAT1_USER_MODE_VALID=y
-CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT2=y
-CONFIG_BAT2_NAME="FLASH"
-CONFIG_BAT2_BASE=0xFE000000
-CONFIG_BAT2_LENGTH_8_MBYTES=y
-CONFIG_BAT2_ACCESS_RW=y
-CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
-CONFIG_BAT2_DCACHE_INHIBITED=y
-CONFIG_BAT2_DCACHE_GUARDED=y
-CONFIG_BAT2_USER_MODE_VALID=y
-CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
-CONFIG_BAT3=y
-CONFIG_BAT3_NAME="STACK_IN_DCACHE"
-CONFIG_BAT3_BASE=0xE6000000
-CONFIG_BAT3_ACCESS_RW=y
-CONFIG_BAT3_USER_MODE_VALID=y
-CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
-CONFIG_LBLAW0=y
-CONFIG_LBLAW0_BASE=0xFE000000
-CONFIG_LBLAW0_NAME="FLASH"
-CONFIG_LBLAW0_LENGTH_8_MBYTES=y
-CONFIG_LBLAW1=y
-CONFIG_LBLAW1_BASE=0xE0600000
-CONFIG_LBLAW1_NAME="FPGA0"
-CONFIG_LBLAW1_LENGTH_1_MBYTES=y
-CONFIG_ELBC_BR0_OR0=y
-CONFIG_BR0_OR0_NAME="FLASH"
-CONFIG_BR0_OR0_BASE=0xFE000000
-CONFIG_BR0_PORTSIZE_16BIT=y
-CONFIG_OR0_AM_8_MBYTES=y
-CONFIG_OR0_XAM_SET=y
-CONFIG_OR0_SCY_15=y
-CONFIG_OR0_CSNT_EARLIER=y
-CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR0_XACS_EXTENDED=y
-CONFIG_OR0_TRLX_RELAXED=y
-CONFIG_OR0_EHTR_8_CYCLE=y
-CONFIG_ELBC_BR1_OR1=y
-CONFIG_BR1_OR1_NAME="FPGA"
-CONFIG_BR1_OR1_BASE=0xE0600000
-CONFIG_BR1_PORTSIZE_16BIT=y
-CONFIG_OR1_AM_1_MBYTES=y
-CONFIG_OR1_XAM_SET=y
-CONFIG_OR1_SCY_15=y
-CONFIG_OR1_CSNT_EARLIER=y
-CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
-CONFIG_OR1_XACS_EXTENDED=y
-CONFIG_OR1_TRLX_RELAXED=y
-CONFIG_OR1_EHTR_8_CYCLE=y
-CONFIG_HID0_FINAL_EMCP=y
-CONFIG_HID0_FINAL_DPM=y
-CONFIG_HID0_FINAL_ICE=y
-CONFIG_HID2_HBE=y
-CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
-CONFIG_SICR_IEEE1588_A_GPIO=y
-CONFIG_SICR_GTM_GPIO=y
-CONFIG_SICR_ETSEC2_GPIO=y
-CONFIG_SICR_GPIOSEL_IEEE1588=y
-CONFIG_SICR_TMSOBI1_2_5_V=y
-CONFIG_SICR_TMSOBI2_2_5_V=y
-CONFIG_ACR_PIPE_DEP_4=y
-CONFIG_ACR_RPTCNT_4=y
-CONFIG_SPCR_TSECEP_3=y
-CONFIG_LCRR_DBYP_PLL_BYPASSED=y
-CONFIG_LCRR_CLKDIV_2=y
-CONFIG_CMD_IOLOOP=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
-CONFIG_BOOTDELAY=5
-CONFIG_USE_PREBOOT=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_FPGAD=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_ENV_ADDR=0xFE060000
-CONFIG_ENV_ADDR_REDUND=0xFE070000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_BITBANGMII=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_MII=y
-CONFIG_TSEC_ENET=y
-CONFIG_CONS_INDEX=2
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
deleted file mode 100644
index ca40417e9a76..000000000000
--- a/include/configs/hrcon.h
+++ /dev/null
@@ -1,421 +0,0 @@ 
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014
- * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1 /* E300 family */
-
-#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
-
-/*
- * SERDES
- */
-#define CONFIG_FSL_SERDES
-#define CONFIG_FSL_SERDES1	0xe3000
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
-#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
-				| DDRCDR_PZ_LOZ \
-				| DDRCDR_NZ_LOZ \
-				| DDRCDR_ODT \
-				| DDRCDR_Q_DRN)
-				/* 0x7b880001 */
-/*
- * Manually set up DDR parameters
- * consist of one chip NT5TU64M16HG from NANYA
- */
-
-#define CONFIG_SYS_DDR_SIZE		128 /* MB */
-
-#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
-				| CSCONFIG_ODT_RD_NEVER \
-				| CSCONFIG_ODT_WR_ONLY_CURRENT \
-				| CSCONFIG_BANK_BIT_3 \
-				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
-				/* 0x80010102 */
-#define CONFIG_SYS_DDR_TIMING_3	0
-#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
-				| (0 << TIMING_CFG0_WRT_SHIFT) \
-				| (0 << TIMING_CFG0_RRT_SHIFT) \
-				| (0 << TIMING_CFG0_WWT_SHIFT) \
-				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
-				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
-				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
-				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
-				/* 0x00260802 */
-#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
-				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
-				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
-				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
-				| (9 << TIMING_CFG1_REFREC_SHIFT) \
-				| (2 << TIMING_CFG1_WRREC_SHIFT) \
-				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
-				| (2 << TIMING_CFG1_WRTORD_SHIFT))
-				/* 0x26279222 */
-#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
-				| (4 << TIMING_CFG2_CPO_SHIFT) \
-				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
-				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
-				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
-				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
-				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
-				/* 0x021848c5 */
-#define CONFIG_SYS_DDR_INTERVAL	((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
-				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
-				/* 0x08240100 */
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
-				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
-				| SDRAM_CFG_DBW_16)
-				/* 0x43100000 */
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
-#define CONFIG_SYS_DDR_MODE		((0x0440 << SDRAM_MODE_ESD_SHIFT) \
-				| (0x0242 << SDRAM_MODE_SD_SHIFT))
-				/* ODT 150ohm CL=4, AL=0 on SDRAM */
-#define CONFIG_SYS_DDR_MODE2		0x00000000
-
-/*
- * Memory test
- */
-
-/*
- * The reserved memory
- */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
-
-/*
- * Initial RAM Base Address Setup
- */
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-/*
- * FLASH on the Local Bus
- */
-#if 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_LEGACY_512Kx16
-#endif
-
-#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
-#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */
-
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	135
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FPGA_DONE(k)		0x0010
-
-#define CONFIG_SYS_FPGA_COUNT		1
-
-#define CONFIG_SYS_MCLINK_MAX		3
-
-#define CONFIG_SYS_FPGA_PTR \
-	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
-
-/*
- * Serial Port
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
-
-/* Pass open firmware flat tree */
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
-
-#define CONFIG_PCA953X			/* NXP PCA9554 */
-#define CONFIG_PCA9698			/* NXP PCA9698 */
-
-#define CONFIG_SYS_I2C_IHS
-#define CONFIG_SYS_I2C_IHS_CH0
-#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
-#define CONFIG_SYS_I2C_IHS_CH1
-#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
-#define CONFIG_SYS_I2C_IHS_CH2
-#define CONFIG_SYS_I2C_IHS_SPEED_2		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_2		0x7F
-#define CONFIG_SYS_I2C_IHS_CH3
-#define CONFIG_SYS_I2C_IHS_SPEED_3		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F
-
-#ifdef CONFIG_HRCON_DH
-#define CONFIG_SYS_I2C_IHS_DUAL
-#define CONFIG_SYS_I2C_IHS_CH0_1
-#define CONFIG_SYS_I2C_IHS_SPEED_0_1		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_0_1		0x7F
-#define CONFIG_SYS_I2C_IHS_CH1_1
-#define CONFIG_SYS_I2C_IHS_SPEED_1_1		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_1_1		0x7F
-#define CONFIG_SYS_I2C_IHS_CH2_1
-#define CONFIG_SYS_I2C_IHS_SPEED_2_1		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_2_1		0x7F
-#define CONFIG_SYS_I2C_IHS_CH3_1
-#define CONFIG_SYS_I2C_IHS_SPEED_3_1		50000
-#define CONFIG_SYS_I2C_IHS_SLAVE_3_1		0x7F
-#endif
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define CONFIG_SYS_I2C_SOFT
-#define CONFIG_SYS_I2C_SOFT_SPEED		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE		0x7F
-#define I2C_SOFT_DECLARATIONS2
-#define CONFIG_SYS_I2C_SOFT_SPEED_2		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_2		0x7F
-#define I2C_SOFT_DECLARATIONS3
-#define CONFIG_SYS_I2C_SOFT_SPEED_3		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_3		0x7F
-#define I2C_SOFT_DECLARATIONS4
-#define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
-#define I2C_SOFT_DECLARATIONS5
-#define CONFIG_SYS_I2C_SOFT_SPEED_5		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_5		0x7F
-#define I2C_SOFT_DECLARATIONS6
-#define CONFIG_SYS_I2C_SOFT_SPEED_6		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_6		0x7F
-#define I2C_SOFT_DECLARATIONS7
-#define CONFIG_SYS_I2C_SOFT_SPEED_7		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_7		0x7F
-#define I2C_SOFT_DECLARATIONS8
-#define CONFIG_SYS_I2C_SOFT_SPEED_8		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_8		0x7F
-
-#ifdef CONFIG_HRCON_DH
-#define I2C_SOFT_DECLARATIONS9
-#define CONFIG_SYS_I2C_SOFT_SPEED_9		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_9		0x7F
-#define I2C_SOFT_DECLARATIONS10
-#define CONFIG_SYS_I2C_SOFT_SPEED_10		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_10		0x7F
-#define I2C_SOFT_DECLARATIONS11
-#define CONFIG_SYS_I2C_SOFT_SPEED_11		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_11		0x7F
-#define I2C_SOFT_DECLARATIONS12
-#define CONFIG_SYS_I2C_SOFT_SPEED_12		50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE_12		0x7F
-#endif
-
-#ifdef CONFIG_HRCON_DH
-#define CONFIG_SYS_ICS8N3QV01_I2C		{13, 14, 15, 16, 17, 18, 19, 20}
-#define CONFIG_SYS_DP501_I2C			{1, 3, 5, 7, 2, 4, 6, 8}
-#define CONFIG_HRCON_FANS			{ {10, 0x4c}, {11, 0x4c}, \
-						  {12, 0x4c} }
-#else
-#define CONFIG_SYS_ICS8N3QV01_I2C		{9, 10, 11, 12}
-#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
-#define CONFIG_HRCON_FANS			{ {6, 0x4c}, {7, 0x4c}, \
-						  {8, 0x4c} }
-#endif
-
-#ifndef __ASSEMBLY__
-void fpga_gpio_set(unsigned int bus, int pin);
-void fpga_gpio_clear(unsigned int bus, int pin);
-int fpga_gpio_get(unsigned int bus, int pin);
-void fpga_control_set(unsigned int bus, int pin);
-void fpga_control_clear(unsigned int bus, int pin);
-#endif
-
-#define I2C_SDA_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
-#define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
-#define I2C_FPGA_IDX	(I2C_ADAP_HWNR % 4)
-
-#ifdef CONFIG_HRCON_DH
-#define I2C_ACTIVE \
-	do { \
-		if (I2C_ADAP_HWNR > 7) \
-			fpga_control_set(I2C_FPGA_IDX, 0x0004); \
-		else \
-			fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
-	} while (0)
-#else
-#define I2C_ACTIVE	{ }
-#endif
-#define I2C_TRISTATE	{ }
-#define I2C_READ \
-	(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
-#define I2C_SDA(bit) \
-	do { \
-		if (bit) \
-			fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
-		else \
-			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
-	} while (0)
-#define I2C_SCL(bit) \
-	do { \
-		if (bit) \
-			fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
-		else \
-			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
-	} while (0)
-#define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
-
-/*
- * Software (bit-bang) MII driver configuration
- */
-#define CONFIG_BITBANGMII_MULTI
-
-/*
- * OSD Setup
- */
-#define CONFIG_SYS_OSD_SCREENS		1
-#define CONFIG_SYS_DP501_DIFFERENTIAL
-#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
-
-#ifdef CONFIG_HRCON_DH
-#define CONFIG_SYS_OSD_DH
-#endif
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCIE1_BASE		0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
-#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
-#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
-
-/* enable PCIE clock */
-#define CONFIG_SYS_SCCR_PCIEXP1CM	1
-
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCIE
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
-#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
-
-/*
- * TSEC
- */
-#define CONFIG_SYS_TSEC1_OFFSET	0x24000
-#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
-
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_TSEC1
-#define CONFIG_TSEC1_NAME	"eTSEC0"
-#define TSEC1_PHY_ADDR		1
-#define TSEC1_PHYIDX		0
-#define TSEC1_FLAGS		TSEC_GIGABIT
-
-/* Options are: eTSEC[0-1] */
-#define CONFIG_ETHPRIME		"eTSEC0"
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
-#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
-
-#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
-
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#endif
-
-#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
-
-
-#define CONFIG_HOSTNAME		"hrcon"
-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"consoledev=ttyS1\0"						\
-	"u-boot=u-boot.bin\0"						\
-	"kernel_addr=1000000\0"					\
-	"fdt_addr=C00000\0"						\
-	"fdtfile=hrcon.dtb\0"				\
-	"load=tftp ${loadaddr} ${u-boot}\0"				\
-	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
-		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
-		" +${filesize};cp.b ${fileaddr} "			\
-		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
-	"upd=run load update\0"						\
-
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv bootargs root=/dev/nfs rw "				\
-	"nfsroot=$serverip:$rootpath "					\
-	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-	"console=$consoledev,$baudrate $othbootargs;"			\
-	"tftp ${kernel_addr} $bootfile;"				\
-	"tftp ${fdt_addr} $fdtfile;"					\
-	"bootm ${kernel_addr} - ${fdt_addr}"
-
-#define CONFIG_MMCBOOTCOMMAND						\
-	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait "		\
-	"console=$consoledev,$baudrate $othbootargs;"			\
-	"ext2load mmc 0:2 ${kernel_addr} $bootfile;"			\
-	"ext2load mmc 0:2 ${fdt_addr} $fdtfile;"			\
-	"bootm ${kernel_addr} - ${fdt_addr}"
-
-#define CONFIG_BOOTCOMMAND		CONFIG_MMCBOOTCOMMAND
-
-#endif	/* __CONFIG_H */
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 1fd646cab1dd..aa9b9f58b810 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -88,50 +88,4 @@  struct ihs_fpga {
 };
 #endif
 
-#if defined(CONFIG_TARGET_HRCON)
-struct ihs_fpga {
-	u16 reflection_low;	/* 0x0000 */
-	u16 versions;		/* 0x0002 */
-	u16 fpga_version;	/* 0x0004 */
-	u16 fpga_features;	/* 0x0006 */
-	u16 reserved_0[1];	/* 0x0008 */
-	u16 top_interrupt;	/* 0x000a */
-	u16 reserved_1[2];	/* 0x000c */
-	u16 control;		/* 0x0010 */
-	u16 extended_control;	/* 0x0012 */
-	struct ihs_gpio gpio;	/* 0x0014 */
-	u16 mpc3w_control;	/* 0x001a */
-	u16 reserved_2[2];	/* 0x001c */
-	struct ihs_io_ep ep;	/* 0x0020 */
-	u16 reserved_3[9];	/* 0x002e */
-	struct ihs_i2c i2c0;	/* 0x0040 */
-	u16 reserved_4[10];	/* 0x004c */
-	u16 mc_int;		/* 0x0060 */
-	u16 mc_int_en;		/* 0x0062 */
-	u16 mc_status;		/* 0x0064 */
-	u16 mc_control;		/* 0x0066 */
-	u16 mc_tx_data;		/* 0x0068 */
-	u16 mc_tx_address;	/* 0x006a */
-	u16 mc_tx_cmd;		/* 0x006c */
-	u16 mc_res;		/* 0x006e */
-	u16 mc_rx_cmd_status;	/* 0x0070 */
-	u16 mc_rx_data;		/* 0x0072 */
-	u16 reserved_5[69];	/* 0x0074 */
-	u16 reflection_high;	/* 0x00fe */
-	struct ihs_osd osd0;	/* 0x0100 */
-#ifdef CONFIG_SYS_OSD_DH
-	u16 reserved_6[57];	/* 0x010e */
-	struct ihs_osd osd1;	/* 0x0180 */
-	u16 reserved_7[9];	/* 0x018e */
-	struct ihs_i2c i2c1;	/* 0x01a0 */
-	u16 reserved_8[1834];	/* 0x01ac */
-	u16 videomem0[2048];	/* 0x1000 */
-	u16 videomem1[2048];	/* 0x2000 */
-#else
-	u16 reserved_6[889];	/* 0x010e */
-	u16 videomem0[2048];	/* 0x0800 */
-#endif
-};
-#endif
-
 #endif