From patchwork Fri Feb 5 04:11:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1436390 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=jy7qlILw; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DX29b6W0fz9sWP for ; Fri, 5 Feb 2021 15:14:11 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5AF0D82A00; Fri, 5 Feb 2021 05:12:34 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="jy7qlILw"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BB134829A1; Fri, 5 Feb 2021 05:12:04 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AA78A829A6 for ; Fri, 5 Feb 2021 05:11:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qv1-xf30.google.com with SMTP id ew18so2885753qvb.4 for ; Thu, 04 Feb 2021 20:11:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=01aziTxuCirc244ie70bIGNVwhnK8z5bLnW6luuFuWo=; b=jy7qlILw143naxUXk+b30+JFPVu8E5hTziojQ6UzJ4vkJTH9Frx8BwCkTCBHCTsHe+ 1VbtBxMIvpI1KIkdwYu8TrXeDgp5/qba3zT9O90twYokvSlqTJRK7KGnD0gQ27oSHxyS FZY4ScpUxC2n0I79Ogy8BKdCd65HZW/epvpzC8qxltDYPbX+sV0u1Aonls0i+TXqWWjG NJHAM36RqpXWa+goBbF6bU+qJoiI/yxswurcBYIyeYpbtElELjLIRKmE8Fs6dZ5ibTqo P4iuZiuyn2cpvs2W/YwIEiebonnESTjLWollmQpwquL5qHkk4EaMd7I8Z6awMdRC+c8I hCug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=01aziTxuCirc244ie70bIGNVwhnK8z5bLnW6luuFuWo=; b=sYPxPxeVQlmvguk70/QVNa4RMrss1S37jmtwlomhgSkel5yLJ97DUgmB70CN7AvJej JsjtHBGavxxe13LiCj87pnT7UjadA0G6+SQqIEWekaamsOo1tny6Km+FUmOrWM80Otsr jeKO9bWve4otIJWKQzCaAV6ewCoZdh8raMaxcyJm/k74CjNH0biUYIQal/AbjErI8tkw Blj2M2T5E+XoZmmeY59E4MXnSoA87sL/vrqqx0SN/VTHKRJAD2Jt76P9TSjDSBOC5vJl 4JNM21CiRAchak/F/nzlut2HpoReEHxTiL/AXHhJRCTcK5zpaJ1TL5rU3jU5az0pIvAg bPBQ== X-Gm-Message-State: AOAM532X0XIOiKADrXkBdsT5/253fnc5cNyaAlGK8iKwvSuIgk6yV1uX URNNEVQS51O0910l3yAv8alcJmXbTjI= X-Google-Smtp-Source: ABdhPJzNtllh62Ilxoeq+3WjLyKCgpxke8onelQr/jsUGwrONnKHN+FuTGdX/5OB9pOvyWM74Ibmwg== X-Received: by 2002:a05:6214:446:: with SMTP id cc6mr2735972qvb.31.1612498309446; Thu, 04 Feb 2021 20:11:49 -0800 (PST) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id y135sm7859758qkb.14.2021.02.04.20.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Feb 2021 20:11:48 -0800 (PST) From: Sean Anderson To: u-boot@lists.denx.de, Jagan Teki Cc: Leo Liang , Pratyush Yadav , Damien Le Moal , Marek Vasut , Sean Anderson Subject: [PATCH v2 13/14] spi: dw: Support clock stretching Date: Thu, 4 Feb 2021 23:11:18 -0500 Message-Id: <20210205041119.145784-14-seanga2@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210205041119.145784-1-seanga2@gmail.com> References: <20210205041119.145784-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean We don't always read/write to the FIFO fast enough. Enable clock stretching for enhanced SPI transfers. This is only possible with DWC SSI devices more recent than 1.01a. We also need to set the RXFTLR register to tell the device when to start reciving again. In particular, the default of 0 will result in the device never restarting reception if there is an overflow. On the transmit side, we need to set CTRL1 so that the device knows when to keep stretching the clock if the FIFO is empty. Signed-off-by: Sean Anderson --- (no changes since v1) drivers/spi/designware_spi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 64a3a8556b..44fb679fdb 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -258,6 +258,7 @@ static u32 dw_spi_update_spi_cr0(const struct spi_mem_op *op) | FIELD_PREP(SPI_CTRLR0_ADDR_L_MASK, op->addr.nbytes * 2) | FIELD_PREP(SPI_CTRLR0_INST_L_MASK, INST_L_8) | FIELD_PREP(SPI_CTRLR0_WAIT_CYCLES_MASK, wait_cycles) + | SPI_CTRLR0_CLK_STRETCH_EN; } static int request_gpio_cs(struct udevice *bus) @@ -360,6 +361,9 @@ static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv) priv->fifo_len = (fifo == 1) ? 0 : fifo; dw_write(priv, DW_SPI_TXFTLR, 0); } + + /* Set receive fifo interrupt level register for clock stretching */ + dw_write(priv, DW_SPI_RXFTLR, priv->fifo_len - 1); } /* @@ -782,8 +786,7 @@ static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) dw_write(priv, DW_SPI_SSIENR, 0); dw_write(priv, DW_SPI_CTRLR0, cr0); - if (read) - dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1); + dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1); if (priv->spi_frf != CTRLR0_SPI_FRF_BYTE) dw_write(priv, DW_SPI_SPI_CTRL0, spi_cr0); dw_write(priv, DW_SPI_SSIENR, 1);