From patchwork Sat Jan 23 18:27:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1430801 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2014 header.b=YSsoz1nf; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DNPkV3vTDz9sVm for ; Sun, 24 Jan 2021 05:27:46 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3276382A08; Sat, 23 Jan 2021 19:27:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="YSsoz1nf"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D45AF82A28; Sat, 23 Jan 2021 19:27:27 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_WEB,SPF_HELO_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-17.italiaonline.it [213.209.10.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 144FC829E6 for ; Sat, 23 Jan 2021 19:27:24 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id 3NczlVbAHbMHl3Nd5ljPVm; Sat, 23 Jan 2021 19:27:23 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1611426443; bh=VC6/Ke2B0dWsbAKspdlCON8rXtX1DriqWS299ydMFwI=; h=From; b=YSsoz1nfsJ4d+i3BYS01u+B/TBa/UYONM3MtttYoHA97+zxP9n3v8YcuCC0mLbkhB LMns7cmrocnZ35DLIeQwOAGsaCMfHwkJQ8yhjBftqCgvmJ8NnUQ9KqDYTq04XBTVlW cGu2YCJAa0cp5PLqfV/YF8mQzpKVn1V2PQ/s/q5R7bULhMXkDeauXuFaIRJFWSXaVm e9QHbwai9JjzoR7whouFe868+WnveRi8xKfYEjazTpIgs22A+NBJJKwDRNXCJCuNrR nhKqyRyTTfv7xa4Day4EvMTeMNe7/z7F7+heTJE8vI0YNbXZxVB8iwtbzulTqDpP/3 OfkZcmHkCdoRQ== X-CNFS-Analysis: v=2.4 cv=Sb8yytdu c=1 sm=1 tr=0 ts=600c6a8b cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=CNNU2WlDxd8r9xRg_hQA:9 a=pHzHmUro8NiASowvMSCR:22 a=6VlIyEUom7LUIeUMNQJH:22 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Andy Shevchenko , Patrick Delaunay , Simon Glass Subject: [PATCH 01/11] pinctrl: single: fix format of structure documentation Date: Sat, 23 Jan 2021 19:27:01 +0100 Message-Id: <20210123182711.7177-2-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210123182711.7177-1-dariobin@libero.it> References: <20210123182711.7177-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfFotGkNhqIDA+cdZzBgXhLAhqpM3CUj4ajzxbJuIV72iEXSOCclEoU7TDhWzpm3RTCdiRQV48SLByJEgUzyF+fbHvNEZNYAieXpVcpvQZHS7NDzaD9zM pJtbw525Leyad1A3TXfFrc3OmskHiUKMSjPMndnkWbTDMpyhuR8V211shhvPboMIWKnmvv53Ep3hOfZ9xdr9b/Ul6XC+ksv9tAeLPZ9YDarbc5XZNiuIvqzT Bs1+HOJjqoPZFP4YzMbjhLOFs1WC/+bWq7yve05gPbyXIeUY0L8KiMd01giebkKi+kQvoouFDuSugprkPIIRQHE+HTQi5RYUIoYZUTqLAynr4fVItIyEJG6x GCXYBkqJibliOvfMKNwQ5u4Rf/zj5O3BhAgnqYDyt0HUPBTphFDPJPtwosrc1LvXylAn60J0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean U-Boot adopted the kernel-doc annotation style. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- drivers/pinctrl/pinctrl-single.c | 45 +++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 20c3c82aa9..c9a6c272bf 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -10,23 +10,50 @@ #include #include +/** + * struct single_pdata - platform data + * @base: first configuration register + * @offset: index of last configuration register + * @mask: configuration-value mask bits + * @width: configuration register bit width + * @bits_per_mux: true if one register controls more than one pin + */ struct single_pdata { - fdt_addr_t base; /* first configuration register */ - int offset; /* index of last configuration register */ - u32 mask; /* configuration-value mask bits */ - int width; /* configuration register bit width */ + fdt_addr_t base; + int offset; + u32 mask; + int width; bool bits_per_mux; }; +/** + * struct single_fdt_pin_cfg - pin configuration + * + * This structure is used for the pin configuration parameters in case + * the register controls only one pin. + * + * @reg: configuration register offset + * @val: configuration register value + */ struct single_fdt_pin_cfg { - fdt32_t reg; /* configuration register offset */ - fdt32_t val; /* configuration register value */ + fdt32_t reg; + fdt32_t val; }; +/** + * struct single_fdt_bits_cfg - pin configuration + * + * This structure is used for the pin configuration parameters in case + * the register controls more than one pin. + * + * @reg: configuration register offset + * @val: configuration register value + * @mask: configuration register mask + */ struct single_fdt_bits_cfg { - fdt32_t reg; /* configuration register offset */ - fdt32_t val; /* configuration register value */ - fdt32_t mask; /* configuration register mask */ + fdt32_t reg; + fdt32_t val; + fdt32_t mask; }; /**