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Tue, 19 Jan 2021 17:01:33 +0000 From: Claudiu Manoil To: Joe Hershberger , Simon Glass , Bin Meng , Michael Walle Cc: u-boot@lists.denx.de, Vladimir Oltean , Alexandru Marginean Subject: [PATCH v2 4/5] arm: dts: ls1028a: Add Ethernet switch node and dependencies Date: Tue, 19 Jan 2021 19:01:09 +0200 Message-Id: <20210119170110.27746-5-claudiu.manoil@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210119170110.27746-1-claudiu.manoil@nxp.com> References: <20210119170110.27746-1-claudiu.manoil@nxp.com> X-Originating-IP: [83.217.231.2] X-ClientProxiedBy: AM0PR02CA0177.eurprd02.prod.outlook.com (2603:10a6:20b:28e::14) To AM0PR04MB6754.eurprd04.prod.outlook.com (2603:10a6:208:170::28) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv15141.swis.ro-buh01.nxp.com (83.217.231.2) by AM0PR02CA0177.eurprd02.prod.outlook.com (2603:10a6:20b:28e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.11 via Frontend Transport; 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The switch node has the same structure as in Linux and this patch enables it (and relevant ports) for the LS1028A RDB board. ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028A, it is not used in U-Boot and was disabled. Ethernet port aliases were also added to better manage the multitude of ports available now. Signed-off-by: Alex Marginean Signed-off-by: Claudiu Manoil --- v2: Switch node structure defined in dtsi now consistent with the Linux switch node definition. Moved aliases from dtsi to the RDB DTS to minimize impact on other boards (and for improved flexibility). arch/arm/dts/fsl-ls1028a-rdb.dts | 63 ++++++++++++++++++++++++++++++++ arch/arm/dts/fsl-ls1028a.dtsi | 56 +++++++++++++++++++++++++++- 2 files changed, 118 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 85b4815b2e..dd35643efc 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -15,6 +15,12 @@ compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; aliases { spi0 = &fspi; + eth0 = &enetc0; + eth1 = &enetc2; + eth2 = &mscc_felix_port0; + eth3 = &mscc_felix_port1; + eth4 = &mscc_felix_port2; + eth5 = &mscc_felix_port3; }; }; @@ -131,9 +137,66 @@ phy-handle = <&rdb_phy0>; }; +&enetc2 { + status = "okay"; +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + label = "swp0"; + phy-handle = <&sw_phy0>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port1 { + label = "swp1"; + phy-handle = <&sw_phy1>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port2 { + label = "swp2"; + phy-handle = <&sw_phy2>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port3 { + label = "swp3"; + phy-handle = <&sw_phy3>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port4 { + ethernet = <&enetc2>; + status = "okay"; +}; + &mdio0 { status = "okay"; rdb_phy0: phy@2 { reg = <2>; }; + + sw_phy0: phy@10 { + reg = <0x10>; + }; + + sw_phy1: phy@11 { + reg = <0x11>; + }; + + sw_phy2: phy@12 { + reg = <0x12>; + }; + + sw_phy3: phy@13 { + reg = <0x13>; + }; }; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index d0850237c7..9740006689 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -151,9 +151,63 @@ reg = <0x000300 0 0 0 0>; status = "disabled"; }; + + mscc_felix: pci@0,5 { + reg = <0x000500 0 0 0 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mscc_felix_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + mscc_felix_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + mscc_felix_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + mscc_felix_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + mscc_felix_port4: port@4 { + reg = <4>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + mscc_felix_port5: port@5 { + reg = <5>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + }; + }; + }; + enetc6: pci@0,6 { reg = <0x000600 0 0 0 0>; - status = "okay"; + status = "disabled"; phy-mode = "internal"; }; };