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[06/12] x86: Update Chromium OS GNVS names

Message ID 20210116145343.6.I6899fb8e644a4342546ee0bfbdd521488635e1ca@changeid
State Superseded
Delegated to: Bin Meng
Headers show
Series x86: Minor improvements mostly for image loading | expand

Commit Message

Simon Glass Jan. 16, 2021, 9:53 p.m. UTC 
The Global Non-Voltatile Storage struct has some fields with particular
meanings. Rename these to make things easier to follow. Also add a few
more boot flags.

GNVS should not be confused with GNVQ (Going Nowhere Very Quickly).

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/intel_gnvs.h | 34 +++++++++++++++++++++++++------
 1 file changed, 28 insertions(+), 6 deletions(-)

Comments

Bin Meng Jan. 21, 2021, 5:37 a.m. UTC | #1 
On Sun, Jan 17, 2021 at 5:54 AM Simon Glass <sjg@chromium.org> wrote:
>
> The Global Non-Voltatile Storage struct has some fields with particular

typo: Volatile

> meanings. Rename these to make things easier to follow. Also add a few
> more boot flags.
>
> GNVS should not be confused with GNVQ (Going Nowhere Very Quickly).
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/intel_gnvs.h | 34 +++++++++++++++++++++++++------
>  1 file changed, 28 insertions(+), 6 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox series

Patch

diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h
index 7f9f101371c..69a20812e5e 100644
--- a/arch/x86/include/asm/intel_gnvs.h
+++ b/arch/x86/include/asm/intel_gnvs.h
@@ -9,6 +9,7 @@ 
 #ifndef _INTEL_GNVS_H_
 #define _INTEL_GNVS_H_
 
+#include <linux/bitops.h>
 /*
  * The chromeos_acpi portion of ACPI GNVS is assumed to live from offset
  * 0x100 - 0x1000.  When defining acpi_global_nvs, use check_member
@@ -18,6 +19,11 @@ 
  */
 #define GNVS_CHROMEOS_ACPI_OFFSET 0x100
 
+enum {
+	BOOT_REASON_OTHER = 0,
+	BOOT_REASON_S3DIAG = 9
+};
+
 enum {
 	CHSW_RECOVERY_X86 =		BIT(1),
 	CHSW_RECOVERY_EC =		BIT(2),
@@ -25,6 +31,22 @@  enum {
 	CHSW_FIRMWARE_WP =		BIT(9),
 };
 
+enum {
+	RECOVERY_REASON_NONE = 0,
+	RECOVERY_REASON_ME = 1
+};
+
+enum {
+	ACTIVE_ECFW_RO = 0,
+	ACTIVE_ECFW_RW = 1
+};
+
+enum {
+	BINF_RECOVERY = 0,
+	BINF_RW_A = 1,
+	BINF_RW_B = 2
+};
+
 enum {
 	FIRMWARE_TYPE_AUTO_DETECT = -1,
 	FIRMWARE_TYPE_RECOVERY = 0,
@@ -40,14 +62,14 @@  struct __packed chromeos_acpi_gnvs {
 	u32	active_main_fw;	/* 04 (0=recovery, 1=A, 2=B) */
 	u32	activeec_fw;	/* 08 (0=RO, 1=RW) */
 	u16	switches;	/* 0c CHSW */
-	u8	vbt4[256];	/* 0e HWID */
-	u8	vbt5[64];	/* 10e FWID */
-	u8	vbt6[64];	/* 14e FRID - 275 */
+	u8	hwid[256];	/* 0e HWID */
+	u8	fwid[64];	/* 10e FWID */
+	u8	frid[64];	/* 14e FRID - 275 */
 	u32	main_fw_type;	/* 18e (2 = developer mode) */
-	u32	vbt8;		/* 192 recovery reason */
-	u32	vbt9;		/* 196 fmap base address */
+	u32	recovery_reason; /* 192 recovery reason */
+	u32	fmap_base;	/* 196 fmap base address */
 	u8	vdat[3072];	/* 19a VDAT space filled by verified boot */
-	u32	vbt10;		/* d9a smbios bios version */
+	u32	fwid_ptr;	/* d9a smbios bios version */
 	u32	mehh[8];	/* d9e management engine hash */
 	u32	ramoops_base;	/* dbe ramoops base address */
 	u32	ramoops_len;	/* dc2 ramoops length */