From patchwork Mon Jan 11 01:03:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1424379 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=arm.com Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DDb813VPRz9sWj for ; Mon, 11 Jan 2021 12:04:17 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4D67682A20; Mon, 11 Jan 2021 02:03:55 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 788A082A1D; Mon, 11 Jan 2021 02:03:52 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 0C79982A17 for ; Mon, 11 Jan 2021 02:03:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 89AEC101E; Sun, 10 Jan 2021 17:03:47 -0800 (PST) Received: from localhost.localdomain (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 480453F66E; Sun, 10 Jan 2021 17:03:46 -0800 (PST) From: Andre Przywara To: Jagan Teki , Jernej Skrabec Cc: Samuel Holland , u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 3/3] net: sun8i-emac: Simplify EPHY offset calculation Date: Mon, 11 Jan 2021 01:03:06 +0000 Message-Id: <20210111010306.6872-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210111010306.6872-1-andre.przywara@arm.com> References: <20210111010306.6872-1-andre.przywara@arm.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Most SoCs using the sun8i-emac IP use a register in the "syscon" area to control some PHY related settings. The R40 is special, since this register is located in the CCU IP. So far we were storing the *base* address in our priv struct, then adding the offset later when we need to use it. Change the code to add the offset already when we parse the DT node, so that sysctl_reg contains the final EPHY register address. This simplifies adding support for the two EMACs on the H616 later. Signed-off-by: Andre Przywara --- drivers/net/sun8i_emac.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index a1a30b34579..38b6b3b08c6 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -324,16 +324,16 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, if (priv->variant == R40_GMAC) { /* Select RGMII for R40 */ - reg = readl(priv->sysctl_reg + 0x164); + reg = readl(priv->sysctl_reg); reg |= SC_ETCS_INT_GMII | SC_EPIT | (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET); - writel(reg, priv->sysctl_reg + 0x164); + writel(reg, priv->sysctl_reg); return 0; } - reg = readl(priv->sysctl_reg + 0x30); + reg = readl(priv->sysctl_reg); reg = sun8i_emac_set_syscon_ephy(priv, reg); @@ -374,7 +374,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET) & SC_ERXDC_MASK; - writel(reg, priv->sysctl_reg + 0x30); + writel(reg, priv->sysctl_reg); return 0; } @@ -916,6 +916,10 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) debug("%s: Cannot find syscon base address\n", __func__); return -EINVAL; } + if (priv->variant == R40_GMAC) + priv->sysctl_reg += 0x164; + else + priv->sysctl_reg += 0x30; pdata->phy_interface = -1; priv->phyaddr = -1;