From patchwork Thu Dec 24 07:25:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1420414 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2014 header.b=arHvmRf5; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D1hX70Csqz9sTc for ; Thu, 24 Dec 2020 18:28:54 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CE4508278F; Thu, 24 Dec 2020 08:27:15 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="arHvmRf5"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D9D8A826FF; Thu, 24 Dec 2020 08:26:37 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-18-i2.italiaonline.it [213.209.12.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D1369826E1 for ; Thu, 24 Dec 2020 08:26:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([79.54.115.44]) by smtp-18.iol.local with ESMTPA id sL0kkruLe7QU9sL10kXLIH; Thu, 24 Dec 2020 08:26:26 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1608794786; bh=B1GuaaSoRPVVcW+SZrbOLJXXBzw+3VBTGmyUIRfk/4k=; h=From; b=arHvmRf57uGqrcR0JuulX3uvZXbKSIxMOWDOfg5TjiF7vW3/se0rv4lxHozwdV91q kJbyNbJHsE5o5F+vbGbkt+uhroMxSpT42gwrB3sR2atQdUcfndRZCE5Ajs/KUjiUZZ nB4FLheLMGQkH+xajr4hUjXnhmkNcMoAKXLu4ZYDqtXQOLVLCQqGmniXjDs2lsqx2m P3/+fxXQ+mvHcn8H4ZeZyPzpCfUOZDoioBznJUNq3n+AOkGTnWddJCLzRdaESOoQ02 whCJjSBOFYI1U0nzHXDI+E9q5IBMnkWco/gjIzdJiyCsqrrGce2+JP5Lq47mewDK6T dpMFMA/EYZYWw== X-CNFS-Analysis: v=2.4 cv=Y+c9DjSN c=1 sm=1 tr=0 ts=5fe442a2 cx=a_exe a=4XFUYcG0DNokufVEFeBjWw==:117 a=4XFUYcG0DNokufVEFeBjWw==:17 a=m0E8M2FGYu1ttQaSf5kA:9 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Lokesh Vutla , Dario Binacchi , Lukasz Majewski Subject: [PATCH v7 10/28] clk: ti: add gate clock driver Date: Thu, 24 Dec 2020 08:25:33 +0100 Message-Id: <20201224072552.15848-11-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201224072552.15848-1-dariobin@libero.it> References: <20201224072552.15848-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfBlyE4804AMdaklwmbkc4oNbqjSFVsOUMTWHzI/uI86hz/ya1R0DxQJ6ALkadUFWHS/1r1hpmt83v06wlXkZ6qCYFz3zL20HXrWl9yyZiUk1k/kw3MH0 THPbbNwLnlDT4Lr+I+ZbEzdE2nVOQeAG+TWMG12QztuDADuxA5qT1NeIrw10NaF8HajN9tRphuC39je9oDv1f6oYQPCozjJaT1EoDgAMZ2mkvMqWNdT+HKUs a4pvjsV7iXHsME0o4PUvyXEe2pzzo6yCt+aJrJKBvz/GY89gOR104xfSjtP72kkthl8BrB/8qgoO7t8M4ZWOrQ== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The patch adds support for TI gate clock binding. The code is based on the drivers/clk/ti/gate.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/gate.txt Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Move the clk-ti-gate.c file to drivers/clk/ti with the name clk-gate.c. Changes in v4: - Include device_compat.h header for dev_xxx macros. Changes in v3: - Remove doc/device-tree-bindings/clock/gpio-gate-clock.txt. - Remove doc/device-tree-bindings/clock/ti,clockdomain.txt. - Remove doc/device-tree-bindings/clock/ti,gate.txt. - Add to commit message the references to linux kernel dt binding documentation. drivers/clk/ti/Kconfig | 6 +++ drivers/clk/ti/Makefile | 1 + drivers/clk/ti/clk-gate.c | 93 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 drivers/clk/ti/clk-gate.c diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig index 87eea86c6f..30959a316a 100644 --- a/drivers/clk/ti/Kconfig +++ b/drivers/clk/ti/Kconfig @@ -16,6 +16,12 @@ config CLK_TI_DIVIDER help This enables the divider clock driver support on TI's SoCs. +config CLK_TI_GATE + bool "TI gate clock driver" + depends on CLK && OF_CONTROL + help + This enables the gate clock driver support on TI's SoCs. + config CLK_TI_MUX bool "TI mux clock driver" depends on CLK && OF_CONTROL && CLK_CCF diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index fd7094cff0..f8aa735c83 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o +obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o diff --git a/drivers/clk/ti/clk-gate.c b/drivers/clk/ti/clk-gate.c new file mode 100644 index 0000000000..6c5432c823 --- /dev/null +++ b/drivers/clk/ti/clk-gate.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TI gate clock support + * + * Copyright (C) 2020 Dario Binacchi + * + * Loosely based on Linux kernel drivers/clk/ti/gate.c + */ + +#include +#include +#include +#include +#include +#include + +struct clk_ti_gate_priv { + fdt_addr_t reg; + u8 enable_bit; + u32 flags; + bool invert_enable; +}; + +static int clk_ti_gate_disable(struct clk *clk) +{ + struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev); + u32 v; + + v = readl(priv->reg); + if (priv->invert_enable) + v |= (1 << priv->enable_bit); + else + v &= ~(1 << priv->enable_bit); + + writel(v, priv->reg); + /* No OCP barrier needed here since it is a disable operation */ + return 0; +} + +static int clk_ti_gate_enable(struct clk *clk) +{ + struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev); + u32 v; + + v = readl(priv->reg); + if (priv->invert_enable) + v &= ~(1 << priv->enable_bit); + else + v |= (1 << priv->enable_bit); + + writel(v, priv->reg); + /* OCP barrier */ + v = readl(priv->reg); + return 0; +} + +static int clk_ti_gate_ofdata_to_platdata(struct udevice *dev) +{ + struct clk_ti_gate_priv *priv = dev_get_priv(dev); + + priv->reg = dev_read_addr(dev); + if (priv->reg == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to get control register\n"); + return -EINVAL; + } + + dev_dbg(dev, "reg=0x%08lx\n", priv->reg); + priv->enable_bit = dev_read_u32_default(dev, "ti,bit-shift", 0); + if (dev_read_bool(dev, "ti,set-rate-parent")) + priv->flags |= CLK_SET_RATE_PARENT; + + priv->invert_enable = dev_read_bool(dev, "ti,set-bit-to-disable"); + return 0; +} + +static struct clk_ops clk_ti_gate_ops = { + .enable = clk_ti_gate_enable, + .disable = clk_ti_gate_disable, +}; + +static const struct udevice_id clk_ti_gate_of_match[] = { + { .compatible = "ti,gate-clock" }, + { }, +}; + +U_BOOT_DRIVER(clk_ti_gate) = { + .name = "ti_gate_clock", + .id = UCLASS_CLK, + .of_match = clk_ti_gate_of_match, + .ofdata_to_platdata = clk_ti_gate_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct clk_ti_gate_priv), + .ops = &clk_ti_gate_ops, +};