From patchwork Fri Dec 11 16:06:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 1415006 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=P4JoMkUi; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Cswm40xwgz9sSs for ; Sat, 12 Dec 2020 03:12:20 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 73D8582748; Fri, 11 Dec 2020 17:08:29 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1607702909; bh=p+VmxxDIwa9EACr/fv8dNJXM64V0uIZQTD0o+9cRDgE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=P4JoMkUizOLM72rmBF3ZgB49wma7rmisYLn8Xx9ergK7tSRtcD03Klef5PtnroTMv x64/4TmfkfBZsbPbWTRRad2VQgRS3m73UcsF5AH97BedgIH1ul11qXGW/kqr0JldgB 9IJCy06AQC8P4bYN+8KWuWVbW//CEKCdxF+TNDJ3myAxpdJlfEobOv0GgyS91BI1It FHKJM1ANatFI2IcPXYRgONabONxeWd+yk/mdSoWceZxj1ZzoHZQ+fu+xBo7Jo1fpFq OimWFg/hWwW6VjP002z6k+WVbwxdfGDqfWWVdjsX+iJl0dr2MEPxzWgcH7zdq/zyG9 FkbthuvJi7tEA== Received: by phobos.denx.de (Postfix, from userid 109) id F0508827AB; Fri, 11 Dec 2020 17:07:56 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mx2.mailbox.org (mx2a.mailbox.org [IPv6:2001:67c:2050:104:0:2:25:2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 601DF8270C for ; Fri, 11 Dec 2020 17:06:28 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de Received: from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mx2.mailbox.org (Postfix) with ESMTPS id 00910A0E3F; Fri, 11 Dec 2020 17:06:27 +0100 (CET) Received: from smtp1.mailbox.org ([80.241.60.240]) by spamfilter04.heinlein-hosting.de (spamfilter04.heinlein-hosting.de [80.241.56.122]) (amavisd-new, port 10030) with ESMTP id KVONrrCqzXkU; Fri, 11 Dec 2020 17:06:24 +0100 (CET) From: Stefan Roese To: u-boot@lists.denx.de Cc: daniel.schwierzeck@gmail.com, awilliams@marvell.com, cchavva@marvell.com Subject: [PATCH v1 38/50] mips: octeon: Add cvmx-helper-jtag.c Date: Fri, 11 Dec 2020 17:06:00 +0100 Message-Id: <20201211160612.1498780-39-sr@denx.de> In-Reply-To: <20201211160612.1498780-1-sr@denx.de> References: <20201211160612.1498780-1-sr@denx.de> MIME-Version: 1.0 X-MBO-SPAM-Probability: X-Rspamd-Score: -0.67 / 15.00 / 15.00 X-Rspamd-Queue-Id: 03C2D1880 X-Rspamd-UID: 47ba48 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Aaron Williams Import cvmx-helper-jtag.c from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/cvmx-helper-jtag.c | 172 +++++++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 arch/mips/mach-octeon/cvmx-helper-jtag.c diff --git a/arch/mips/mach-octeon/cvmx-helper-jtag.c b/arch/mips/mach-octeon/cvmx-helper-jtag.c new file mode 100644 index 0000000000..a6fa69b4c5 --- /dev/null +++ b/arch/mips/mach-octeon/cvmx-helper-jtag.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Marvell International Ltd. + * + * Helper utilities for qlm_jtag. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/** + * Initialize the internal QLM JTAG logic to allow programming + * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions. + * These functions should only be used at the direction of Cavium + * Networks. Programming incorrect values into the JTAG chain + * can cause chip damage. + */ +void cvmx_helper_qlm_jtag_init(void) +{ + union cvmx_ciu_qlm_jtgc jtgc; + int clock_div = 0; + int divisor; + + divisor = gd->bus_clk / (1000000 * (OCTEON_IS_MODEL(OCTEON_CN68XX) ? 10 : 25)); + + divisor = (divisor - 1) >> 2; + /* Convert the divisor into a power of 2 shift */ + while (divisor) { + clock_div++; + divisor >>= 1; + } + + /* + * Clock divider for QLM JTAG operations. sclk is divided by + * 2^(CLK_DIV + 2) + */ + jtgc.u64 = 0; + jtgc.s.clk_div = clock_div; + jtgc.s.mux_sel = 0; + if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)) + jtgc.s.bypass = 0x7; + else + jtgc.s.bypass = 0xf; + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + jtgc.s.bypass_ext = 1; + csr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64); + csr_rd(CVMX_CIU_QLM_JTGC); +} + +/** + * Write up to 32bits into the QLM jtag chain. Bits are shifted + * into the MSB and out the LSB, so you should shift in the low + * order bits followed by the high order bits. The JTAG chain for + * CN52XX and CN56XX is 4 * 268 bits long, or 1072. The JTAG chain + * for CN63XX is 4 * 300 bits long, or 1200. + * + * @param qlm QLM to shift value into + * @param bits Number of bits to shift in (1-32). + * @param data Data to shift in. Bit 0 enters the chain first, followed by + * bit 1, etc. + * + * @return The low order bits of the JTAG chain that shifted out of the + * circle. + */ +uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data) +{ + union cvmx_ciu_qlm_jtgc jtgc; + union cvmx_ciu_qlm_jtgd jtgd; + + jtgc.u64 = csr_rd(CVMX_CIU_QLM_JTGC); + jtgc.s.mux_sel = qlm; + csr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64); + csr_rd(CVMX_CIU_QLM_JTGC); + + jtgd.u64 = 0; + jtgd.s.shift = 1; + jtgd.s.shft_cnt = bits - 1; + jtgd.s.shft_reg = data; + jtgd.s.select = 1 << qlm; + csr_wr(CVMX_CIU_QLM_JTGD, jtgd.u64); + do { + jtgd.u64 = csr_rd(CVMX_CIU_QLM_JTGD); + } while (jtgd.s.shift); + return jtgd.s.shft_reg >> (32 - bits); +} + +/** + * Shift long sequences of zeros into the QLM JTAG chain. It is + * common to need to shift more than 32 bits of zeros into the + * chain. This function is a convience wrapper around + * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of + * zeros at a time. + * + * @param qlm QLM to shift zeros into + * @param bits + */ +void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits) +{ + while (bits > 0) { + int n = bits; + + if (n > 32) + n = 32; + cvmx_helper_qlm_jtag_shift(qlm, n, 0); + bits -= n; + } +} + +/** + * Program the QLM JTAG chain into all lanes of the QLM. You must + * have already shifted in the proper number of bits into the + * JTAG chain. Updating invalid values can possibly cause chip damage. + * + * @param qlm QLM to program + */ +void cvmx_helper_qlm_jtag_update(int qlm) +{ + union cvmx_ciu_qlm_jtgc jtgc; + union cvmx_ciu_qlm_jtgd jtgd; + + jtgc.u64 = csr_rd(CVMX_CIU_QLM_JTGC); + jtgc.s.mux_sel = qlm; + + csr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64); + csr_rd(CVMX_CIU_QLM_JTGC); + + /* Update the new data */ + jtgd.u64 = 0; + jtgd.s.update = 1; + jtgd.s.select = 1 << qlm; + csr_wr(CVMX_CIU_QLM_JTGD, jtgd.u64); + do { + jtgd.u64 = csr_rd(CVMX_CIU_QLM_JTGD); + } while (jtgd.s.update); +} + +/** + * Load the QLM JTAG chain with data from all lanes of the QLM. + * + * @param qlm QLM to program + */ +void cvmx_helper_qlm_jtag_capture(int qlm) +{ + union cvmx_ciu_qlm_jtgc jtgc; + union cvmx_ciu_qlm_jtgd jtgd; + + jtgc.u64 = csr_rd(CVMX_CIU_QLM_JTGC); + jtgc.s.mux_sel = qlm; + + csr_wr(CVMX_CIU_QLM_JTGC, jtgc.u64); + csr_rd(CVMX_CIU_QLM_JTGC); + + jtgd.u64 = 0; + jtgd.s.capture = 1; + jtgd.s.select = 1 << qlm; + csr_wr(CVMX_CIU_QLM_JTGD, jtgd.u64); + do { + jtgd.u64 = csr_rd(CVMX_CIU_QLM_JTGD); + } while (jtgd.s.capture); +}