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Wed, 2 Dec 2020 18:01:35 +0000 From: Andrey Zhizhikin To: u-boot@lists.denx.de Cc: Stefano Babic , Ye Li Subject: [PATCH v2 2/2] ARM: dts: imx8m: add UHS or HS400/HS400ES properties Date: Wed, 2 Dec 2020 18:01:21 +0000 Message-Id: <20201202180121.11550-1-andrey.zhizhikin@leica-geosystems.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201201085821.23050-3-andrey.zhizhikin@leica-geosystems.com> References: <20201201085821.23050-3-andrey.zhizhikin@leica-geosystems.com> X-Originating-IP: [193.8.40.112] X-ClientProxiedBy: ZR0P278CA0122.CHEP278.PROD.OUTLOOK.COM (2603:10a6:910:20::19) To DB6PR0602MB2886.eurprd06.prod.outlook.com (2603:10a6:4:9b::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from aherlnxbspsrv01.lgs-net.com (193.8.40.112) by ZR0P278CA0122.CHEP278.PROD.OUTLOOK.COM (2603:10a6:910:20::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.18 via Frontend Transport; Wed, 2 Dec 2020 18:01:35 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 40b0fb94-7ff3-46c6-28c5-08d896ec4f25 X-MS-TrafficTypeDiagnostic: DB6PR0602MB2887: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:172; 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Enable this support across the entire i.MX8M family by providing quirks to usdhc controllers designated by storage media connected to them. Signed-off-by: Andrey Zhizhikin Cc: Stefano Babic Cc: Ye Li --- Changes in v2: - Moved u-boot binding for imx8mq-evk to separate autoincluded dtsi files arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 3 +++ arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 3 +++ arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 4 ++++ arch/arm/dts/imx8mq-evk-u-boot.dtsi | 9 +++++++++ 6 files changed, 27 insertions(+) diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index 80d6475b7c..2f86fcce3e 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -118,8 +118,11 @@ &usdhc1 { u-boot,dm-spl; + u-boot,mmc-hs400-1_8v; }; &usdhc2 { u-boot,dm-spl; + u-boot,sd-uhs-sdr104; + u-boot,sd-uhs-ddr50; }; diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi index 771ab635f1..f4332edac5 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi @@ -118,8 +118,11 @@ &usdhc1 { u-boot,dm-spl; + u-boot,mmc-hs400-1_8v; }; &usdhc2 { u-boot,dm-spl; + u-boot,sd-uhs-sdr104; + u-boot,sd-uhs-ddr50; }; diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 9f77d3c6ff..67666a08ec 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -100,10 +100,14 @@ &usdhc2 { u-boot,dm-spl; + u-boot,sd-uhs-sdr104; + u-boot,sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + u-boot,mmc-hs400-1_8v; + u-boot,mmc-hs400-enhanced-strobe; }; &i2c1 { diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 98b0b9891b..e03e635213 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -97,10 +97,14 @@ &usdhc2 { u-boot,dm-spl; + u-boot,sd-uhs-sdr104; + u-boot,sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + u-boot,mmc-hs400-1_8v; + u-boot,mmc-hs400-enhanced-strobe; }; &wdog1 { diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 2452e9175c..0776b24a6e 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -126,10 +126,14 @@ &usdhc2 { u-boot,dm-spl; + u-boot,sd-uhs-sdr104; + u-boot,sd-uhs-ddr50; }; &usdhc3 { u-boot,dm-spl; + u-boot,mmc-hs400-1_8v; + u-boot,mmc-hs400-enhanced-strobe; }; &wdog1 { diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi index 4712cf6a44..d0fc64c433 100644 --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -3,3 +3,12 @@ ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; }; + +&usdhc1 { + u-boot,mmc-hs400-1_8v; +}; + +&usdhc2 { + u-boot,sd-uhs-sdr104; + u-boot,sd-uhs-ddr50; +};