From patchwork Sun Nov 22 16:16:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1404520 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2014 header.b=esYQtCHS; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CfFpv3M2jz9sSf for ; Mon, 23 Nov 2020 03:19:19 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 09409825FF; Sun, 22 Nov 2020 17:17:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="esYQtCHS"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 04871825EC; Sun, 22 Nov 2020 17:17:33 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,FREEMAIL_FROM,KHOP_HELO_FCRDNS,T_SPF_HELO_TEMPERROR autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-31.italiaonline.it [213.209.10.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C3508825A1 for ; Sun, 22 Nov 2020 17:17:11 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.2.94.187]) by smtp-31.iol.local with ESMTPA id gs31kH3pbQgqqgs35knAxd; Sun, 22 Nov 2020 17:17:11 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1606061831; bh=YICVR3wHVu1xlw7tPR8XHgLxF8ixcTf02a77Wv0Sh0Y=; h=From; b=esYQtCHSUH437DDXQZD+kbNPiug6k3abK00d+VJPXpkhB3eOJxCXJONtfjFJShu2E oIwmbpwCEdnofOzfZALYj7X2ETv+1/yog7YMANVRJEaE22BQPEpnoKcp454TQqPn8R LoxS2qliymzrQBieqnCZcyaR2iDYxUirhKDpPzPcUEQohOPZAfvs9BPP9t//dDnMb7 fZUN1adaqslrGCv3/+gnOHdU6djy5eyAvewIUj+NS8qQSLjeX1tQK3uasxTR8PlMkZ nsY3IGlLuWpCCYPK/mntmB+Gki/43l9JrIOxXYPa/JesXbCLlZenCBUlagLUql7fNF 9tLyLJ73j5LVA== X-CNFS-Analysis: v=2.4 cv=K4fnowaI c=1 sm=1 tr=0 ts=5fba8f07 a=/8YHF75YQ9f7f3UrJFxoKA==:117 a=/8YHF75YQ9f7f3UrJFxoKA==:17 a=ayfQt84TMKRk2S_j55sA:9 a=1Jk6HBuy0_d3h58u:21 a=352KMiGVTdISc_wO:21 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Dario Binacchi , Heiko Schocher , Neil Armstrong , Sam Shih , Yash Shah Subject: [PATCH v6 20/28] pwm: ti: am33xx: add enhanced pwm driver Date: Sun, 22 Nov 2020 17:16:28 +0100 Message-Id: <20201122161636.14587-21-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201122161636.14587-19-dariobin@libero.it> References: <20201122161636.14587-19-dariobin@libero.it> X-CMAE-Envelope: MS4xfATJa6t/8jUHubyCpCOhQQJx3mMkwOsveMM7je8tMx6sAZmJVdRcBWOBczoshL//5XhOJL5MngDjDt+JiGsdxgr0SmYXN9oHUHc92J2ZxNlBCUUEBEhd 4RCETuI4phf3bugaeqhvznR5xYXug/XMAUvaS6r5seNC5NdZxT//71XWW7DibeWVKvA6q9mSw330EIkP7mGw1V8/hzQeicHcIrdcV4ZUse/fyEaMw3oTm7F9 TFBLdCI8+yxsF0JWQYlMUUobtn1ag39c8PIOOfOaSy1KldvmFy92T+5Z7KTAHY1NgYelU9cufAKu9qjAQEz2jVwBTTzZVbxNQv1eOcokMZFN92oD4H82YE5K axmKtmyKQFa6/Oqd3UmZOZLFU9nKAw== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Enhanced high resolution PWM module (EHRPWM) hardware can be used to generate PWM output over 2 channels. This commit adds PWM driver support for EHRPWM device present on AM33XX SOC. The code is based on the drivers/pwm/pwm-tiehrpwm.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - Include device_compat.h header for dev_xxx macros. Changes in v3: - Adds PWM_TI_EHRPWM dependency on ARCH_OMAP2PLUS in Kconfig. - Add error message in case of invalid address. - Remove doc/device-tree-bindings/pwm/ti,ehrpwm.txt. - Add to commit message the references to linux kernel dt binding documentation. drivers/pwm/Kconfig | 7 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ti-ehrpwm.c | 468 ++++++++++++++++++++++++++++++++++++ 3 files changed, 476 insertions(+) create mode 100644 drivers/pwm/pwm-ti-ehrpwm.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index b3bd5c6bb7..ccf81abbe9 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -75,3 +75,10 @@ config PWM_SUNXI help This PWM is found on H3, A64 and other Allwinner SoCs. It supports a programmable period and duty cycle. A 16-bit counter is used. + +config PWM_TI_EHRPWM + bool "Enable support for EHRPWM PWM" + depends on DM_PWM && ARCH_OMAP2PLUS + default y + help + PWM driver support for the EHRPWM controller found on TI SOCs. diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index f21ae7d76e..0b9d2698a3 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -19,3 +19,4 @@ obj-$(CONFIG_PWM_SANDBOX) += sandbox_pwm.o obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o obj-$(CONFIG_PWM_SUNXI) += sunxi_pwm.o +obj-$(CONFIG_PWM_TI_EHRPWM) += pwm-ti-ehrpwm.o diff --git a/drivers/pwm/pwm-ti-ehrpwm.c b/drivers/pwm/pwm-ti-ehrpwm.c new file mode 100644 index 0000000000..df995c8865 --- /dev/null +++ b/drivers/pwm/pwm-ti-ehrpwm.c @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * EHRPWM PWM driver + * + * Copyright (C) 2020 Dario Binacchi + * + * Based on Linux kernel drivers/pwm/pwm-tiehrpwm.c + */ + +#include +#include +#include +#include +#include +#include +#include + +#define NSEC_PER_SEC 1000000000L + +/* Time base module registers */ +#define TI_EHRPWM_TBCTL 0x00 +#define TI_EHRPWM_TBPRD 0x0A + +#define TI_EHRPWM_TBCTL_PRDLD_MASK BIT(3) +#define TI_EHRPWM_TBCTL_PRDLD_SHDW 0 +#define TI_EHRPWM_TBCTL_PRDLD_IMDT BIT(3) +#define TI_EHRPWM_TBCTL_CLKDIV_MASK GENMASK(12, 7) +#define TI_EHRPWM_TBCTL_CTRMODE_MASK GENMASK(1, 0) +#define TI_EHRPWM_TBCTL_CTRMODE_UP 0 +#define TI_EHRPWM_TBCTL_CTRMODE_DOWN BIT(0) +#define TI_EHRPWM_TBCTL_CTRMODE_UPDOWN BIT(1) +#define TI_EHRPWM_TBCTL_CTRMODE_FREEZE GENMASK(1, 0) + +#define TI_EHRPWM_TBCTL_HSPCLKDIV_SHIFT 7 +#define TI_EHRPWM_TBCTL_CLKDIV_SHIFT 10 + +#define TI_EHRPWM_CLKDIV_MAX 7 +#define TI_EHRPWM_HSPCLKDIV_MAX 7 +#define TI_EHRPWM_PERIOD_MAX 0xFFFF + +/* Counter compare module registers */ +#define TI_EHRPWM_CMPA 0x12 +#define TI_EHRPWM_CMPB 0x14 + +/* Action qualifier module registers */ +#define TI_EHRPWM_AQCTLA 0x16 +#define TI_EHRPWM_AQCTLB 0x18 +#define TI_EHRPWM_AQSFRC 0x1A +#define TI_EHRPWM_AQCSFRC 0x1C + +#define TI_EHRPWM_AQCTL_CBU_MASK GENMASK(9, 8) +#define TI_EHRPWM_AQCTL_CBU_FRCLOW BIT(8) +#define TI_EHRPWM_AQCTL_CBU_FRCHIGH BIT(9) +#define TI_EHRPWM_AQCTL_CBU_FRCTOGGLE GENMASK(9, 8) +#define TI_EHRPWM_AQCTL_CAU_MASK GENMASK(5, 4) +#define TI_EHRPWM_AQCTL_CAU_FRCLOW BIT(4) +#define TI_EHRPWM_AQCTL_CAU_FRCHIGH BIT(5) +#define TI_EHRPWM_AQCTL_CAU_FRCTOGGLE GENMASK(5, 4) +#define TI_EHRPWM_AQCTL_PRD_MASK GENMASK(3, 2) +#define TI_EHRPWM_AQCTL_PRD_FRCLOW BIT(2) +#define TI_EHRPWM_AQCTL_PRD_FRCHIGH BIT(3) +#define TI_EHRPWM_AQCTL_PRD_FRCTOGGLE GENMASK(3, 2) +#define TI_EHRPWM_AQCTL_ZRO_MASK GENMASK(1, 0) +#define TI_EHRPWM_AQCTL_ZRO_FRCLOW BIT(0) +#define TI_EHRPWM_AQCTL_ZRO_FRCHIGH BIT(1) +#define TI_EHRPWM_AQCTL_ZRO_FRCTOGGLE GENMASK(1, 0) + +#define TI_EHRPWM_AQCTL_CHANA_POLNORMAL (TI_EHRPWM_AQCTL_CAU_FRCLOW | \ + TI_EHRPWM_AQCTL_PRD_FRCHIGH | \ + TI_EHRPWM_AQCTL_ZRO_FRCHIGH) +#define TI_EHRPWM_AQCTL_CHANA_POLINVERSED (TI_EHRPWM_AQCTL_CAU_FRCHIGH | \ + TI_EHRPWM_AQCTL_PRD_FRCLOW | \ + TI_EHRPWM_AQCTL_ZRO_FRCLOW) +#define TI_EHRPWM_AQCTL_CHANB_POLNORMAL (TI_EHRPWM_AQCTL_CBU_FRCLOW | \ + TI_EHRPWM_AQCTL_PRD_FRCHIGH | \ + TI_EHRPWM_AQCTL_ZRO_FRCHIGH) +#define TI_EHRPWM_AQCTL_CHANB_POLINVERSED (TI_EHRPWM_AQCTL_CBU_FRCHIGH | \ + TI_EHRPWM_AQCTL_PRD_FRCLOW | \ + TI_EHRPWM_AQCTL_ZRO_FRCLOW) + +#define TI_EHRPWM_AQSFRC_RLDCSF_MASK GENMASK(7, 6) +#define TI_EHRPWM_AQSFRC_RLDCSF_ZRO 0 +#define TI_EHRPWM_AQSFRC_RLDCSF_PRD BIT(6) +#define TI_EHRPWM_AQSFRC_RLDCSF_ZROPRD BIT(7) +#define TI_EHRPWM_AQSFRC_RLDCSF_IMDT GENMASK(7, 6) + +#define TI_EHRPWM_AQCSFRC_CSFB_MASK GENMASK(3, 2) +#define TI_EHRPWM_AQCSFRC_CSFB_FRCDIS 0 +#define TI_EHRPWM_AQCSFRC_CSFB_FRCLOW BIT(2) +#define TI_EHRPWM_AQCSFRC_CSFB_FRCHIGH BIT(3) +#define TI_EHRPWM_AQCSFRC_CSFB_DISSWFRC GENMASK(3, 2) +#define TI_EHRPWM_AQCSFRC_CSFA_MASK GENMASK(1, 0) +#define TI_EHRPWM_AQCSFRC_CSFA_FRCDIS 0 +#define TI_EHRPWM_AQCSFRC_CSFA_FRCLOW BIT(0) +#define TI_EHRPWM_AQCSFRC_CSFA_FRCHIGH BIT(1) +#define TI_EHRPWM_AQCSFRC_CSFA_DISSWFRC GENMASK(1, 0) + +#define TI_EHRPWM_NUM_CHANNELS 2 + +struct ti_ehrpwm_priv { + fdt_addr_t regs; + u32 clk_rate; + struct clk tbclk; + unsigned long period_cycles[TI_EHRPWM_NUM_CHANNELS]; + bool polarity_reversed[TI_EHRPWM_NUM_CHANNELS]; +}; + +static void ti_ehrpwm_modify(u16 val, u16 mask, fdt_addr_t reg) +{ + unsigned short v; + + v = readw(reg); + v &= ~mask; + v |= val & mask; + writew(v, reg); +} + +static int ti_ehrpwm_set_invert(struct udevice *dev, uint channel, + bool polarity) +{ + struct ti_ehrpwm_priv *priv = dev_get_priv(dev); + + if (channel >= TI_EHRPWM_NUM_CHANNELS) + return -ENOSPC; + + /* Configuration of polarity in hardware delayed, do at enable */ + priv->polarity_reversed[channel] = polarity; + return 0; +} + +/** + * set_prescale_div - Set up the prescaler divider function + * @rqst_prescaler: prescaler value min + * @prescale_div: prescaler value set + * @tb_clk_div: Time Base Control prescaler bits + */ +static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div, + u16 *tb_clk_div) +{ + unsigned int clkdiv, hspclkdiv; + + for (clkdiv = 0; clkdiv <= TI_EHRPWM_CLKDIV_MAX; clkdiv++) { + for (hspclkdiv = 0; hspclkdiv <= TI_EHRPWM_HSPCLKDIV_MAX; + hspclkdiv++) { + /* + * calculations for prescaler value : + * prescale_div = HSPCLKDIVIDER * CLKDIVIDER. + * HSPCLKDIVIDER = 2 ** hspclkdiv + * CLKDIVIDER = (1), if clkdiv == 0 *OR* + * (2 * clkdiv), if clkdiv != 0 + * + * Configure prescale_div value such that period + * register value is less than 65535. + */ + + *prescale_div = (1 << clkdiv) * + (hspclkdiv ? (hspclkdiv * 2) : 1); + if (*prescale_div > rqst_prescaler) { + *tb_clk_div = + (clkdiv << TI_EHRPWM_TBCTL_CLKDIV_SHIFT) | + (hspclkdiv << + TI_EHRPWM_TBCTL_HSPCLKDIV_SHIFT); + return 0; + } + } + } + + return 1; +} + +static void ti_ehrpwm_configure_polarity(struct udevice *dev, uint channel) +{ + struct ti_ehrpwm_priv *priv = dev_get_priv(dev); + u16 aqctl_val, aqctl_mask; + unsigned int aqctl_reg; + + /* + * Configure PWM output to HIGH/LOW level on counter + * reaches compare register value and LOW/HIGH level + * on counter value reaches period register value and + * zero value on counter + */ + if (channel == 1) { + aqctl_reg = TI_EHRPWM_AQCTLB; + aqctl_mask = TI_EHRPWM_AQCTL_CBU_MASK; + + if (priv->polarity_reversed[channel]) + aqctl_val = TI_EHRPWM_AQCTL_CHANB_POLINVERSED; + else + aqctl_val = TI_EHRPWM_AQCTL_CHANB_POLNORMAL; + } else { + aqctl_reg = TI_EHRPWM_AQCTLA; + aqctl_mask = TI_EHRPWM_AQCTL_CAU_MASK; + + if (priv->polarity_reversed[channel]) + aqctl_val = TI_EHRPWM_AQCTL_CHANA_POLINVERSED; + else + aqctl_val = TI_EHRPWM_AQCTL_CHANA_POLNORMAL; + } + + aqctl_mask |= TI_EHRPWM_AQCTL_PRD_MASK | TI_EHRPWM_AQCTL_ZRO_MASK; + ti_ehrpwm_modify(aqctl_val, aqctl_mask, priv->regs + aqctl_reg); +} + +/* + * period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE + * duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE + */ +static int ti_ehrpwm_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct ti_ehrpwm_priv *priv = dev_get_priv(dev); + u32 period_cycles, duty_cycles; + u16 ps_divval, tb_divval; + unsigned int i, cmp_reg; + unsigned long long c; + + if (channel >= TI_EHRPWM_NUM_CHANNELS) + return -ENOSPC; + + if (period_ns > NSEC_PER_SEC) + return -ERANGE; + + c = priv->clk_rate; + c = c * period_ns; + do_div(c, NSEC_PER_SEC); + period_cycles = (unsigned long)c; + + if (period_cycles < 1) { + period_cycles = 1; + duty_cycles = 1; + } else { + c = priv->clk_rate; + c = c * duty_ns; + do_div(c, NSEC_PER_SEC); + duty_cycles = (unsigned long)c; + } + + dev_dbg(dev, "channel=%d, period_ns=%d, duty_ns=%d\n", + channel, period_ns, duty_ns); + + /* + * Period values should be same for multiple PWM channels as IP uses + * same period register for multiple channels. + */ + for (i = 0; i < TI_EHRPWM_NUM_CHANNELS; i++) { + if (priv->period_cycles[i] && + priv->period_cycles[i] != period_cycles) { + /* + * Allow channel to reconfigure period if no other + * channels being configured. + */ + if (i == channel) + continue; + + dev_err(dev, "period value conflicts with channel %u\n", + i); + return -EINVAL; + } + } + + priv->period_cycles[channel] = period_cycles; + + /* Configure clock prescaler to support Low frequency PWM wave */ + if (set_prescale_div(period_cycles / TI_EHRPWM_PERIOD_MAX, &ps_divval, + &tb_divval)) { + dev_err(dev, "unsupported values\n"); + return -EINVAL; + } + + /* Update clock prescaler values */ + ti_ehrpwm_modify(tb_divval, TI_EHRPWM_TBCTL_CLKDIV_MASK, + priv->regs + TI_EHRPWM_TBCTL); + + /* Update period & duty cycle with presacler division */ + period_cycles = period_cycles / ps_divval; + duty_cycles = duty_cycles / ps_divval; + + /* Configure shadow loading on Period register */ + ti_ehrpwm_modify(TI_EHRPWM_TBCTL_PRDLD_SHDW, TI_EHRPWM_TBCTL_PRDLD_MASK, + priv->regs + TI_EHRPWM_TBCTL); + + writew(period_cycles, priv->regs + TI_EHRPWM_TBPRD); + + /* Configure ehrpwm counter for up-count mode */ + ti_ehrpwm_modify(TI_EHRPWM_TBCTL_CTRMODE_UP, + TI_EHRPWM_TBCTL_CTRMODE_MASK, + priv->regs + TI_EHRPWM_TBCTL); + + if (channel == 1) + /* Channel 1 configured with compare B register */ + cmp_reg = TI_EHRPWM_CMPB; + else + /* Channel 0 configured with compare A register */ + cmp_reg = TI_EHRPWM_CMPA; + + writew(duty_cycles, priv->regs + cmp_reg); + return 0; +} + +static int ti_ehrpwm_disable(struct udevice *dev, uint channel) +{ + struct ti_ehrpwm_priv *priv = dev_get_priv(dev); + u16 aqcsfrc_val, aqcsfrc_mask; + int err; + + if (channel >= TI_EHRPWM_NUM_CHANNELS) + return -ENOSPC; + + /* Action Qualifier puts PWM output low forcefully */ + if (channel) { + aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFB_FRCLOW; + aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFB_MASK; + } else { + aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFA_FRCLOW; + aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFA_MASK; + } + + /* Update shadow register first before modifying active register */ + ti_ehrpwm_modify(TI_EHRPWM_AQSFRC_RLDCSF_ZRO, + TI_EHRPWM_AQSFRC_RLDCSF_MASK, + priv->regs + TI_EHRPWM_AQSFRC); + + ti_ehrpwm_modify(aqcsfrc_val, aqcsfrc_mask, + priv->regs + TI_EHRPWM_AQCSFRC); + + /* + * Changes to immediate action on Action Qualifier. This puts + * Action Qualifier control on PWM output from next TBCLK + */ + ti_ehrpwm_modify(TI_EHRPWM_AQSFRC_RLDCSF_IMDT, + TI_EHRPWM_AQSFRC_RLDCSF_MASK, + priv->regs + TI_EHRPWM_AQSFRC); + + ti_ehrpwm_modify(aqcsfrc_val, aqcsfrc_mask, + priv->regs + TI_EHRPWM_AQCSFRC); + + /* Disabling TBCLK on PWM disable */ + err = clk_disable(&priv->tbclk); + if (err) { + dev_err(dev, "failed to disable tbclk\n"); + return err; + } + + return 0; +} + +static int ti_ehrpwm_enable(struct udevice *dev, uint channel) +{ + struct ti_ehrpwm_priv *priv = dev_get_priv(dev); + u16 aqcsfrc_val, aqcsfrc_mask; + int err; + + if (channel >= TI_EHRPWM_NUM_CHANNELS) + return -ENOSPC; + + /* Disabling Action Qualifier on PWM output */ + if (channel) { + aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFB_FRCDIS; + aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFB_MASK; + } else { + aqcsfrc_val = TI_EHRPWM_AQCSFRC_CSFA_FRCDIS; + aqcsfrc_mask = TI_EHRPWM_AQCSFRC_CSFA_MASK; + } + + /* Changes to shadow mode */ + ti_ehrpwm_modify(TI_EHRPWM_AQSFRC_RLDCSF_ZRO, + TI_EHRPWM_AQSFRC_RLDCSF_MASK, + priv->regs + TI_EHRPWM_AQSFRC); + + ti_ehrpwm_modify(aqcsfrc_val, aqcsfrc_mask, + priv->regs + TI_EHRPWM_AQCSFRC); + + /* Channels polarity can be configured from action qualifier module */ + ti_ehrpwm_configure_polarity(dev, channel); + + err = clk_enable(&priv->tbclk); + if (err) { + dev_err(dev, "failed to enable tbclk\n"); + return err; + } + + return 0; +} + +static int ti_ehrpwm_set_enable(struct udevice *dev, uint channel, bool enable) +{ + if (enable) + return ti_ehrpwm_enable(dev, channel); + + return ti_ehrpwm_disable(dev, channel); +} + +static int ti_ehrpwm_ofdata_to_platdata(struct udevice *dev) +{ + struct ti_ehrpwm_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr(dev); + if (priv->regs == FDT_ADDR_T_NONE) { + dev_err(dev, "invalid address\n"); + return -EINVAL; + } + + dev_dbg(dev, "regs=0x%08lx\n", priv->regs); + return 0; +} + +static int ti_ehrpwm_remove(struct udevice *dev) +{ + struct ti_ehrpwm_priv *priv = dev_get_priv(dev); + + clk_release_all(&priv->tbclk, 1); + return 0; +} + +static int ti_ehrpwm_probe(struct udevice *dev) +{ + struct ti_ehrpwm_priv *priv = dev_get_priv(dev); + struct clk clk; + int err; + + err = clk_get_by_name(dev, "fck", &clk); + if (err) { + dev_err(dev, "failed to get clock\n"); + return err; + } + + priv->clk_rate = clk_get_rate(&clk); + if (IS_ERR_VALUE(priv->clk_rate) || !priv->clk_rate) { + dev_err(dev, "failed to get clock rate\n"); + if (IS_ERR_VALUE(priv->clk_rate)) + return priv->clk_rate; + + return -EINVAL; + } + + /* Acquire tbclk for Time Base EHRPWM submodule */ + err = clk_get_by_name(dev, "tbclk", &priv->tbclk); + if (err) { + dev_err(dev, "failed to get tbclk clock\n"); + return err; + } + + return 0; +} + +static const struct pwm_ops ti_ehrpwm_ops = { + .set_config = ti_ehrpwm_set_config, + .set_enable = ti_ehrpwm_set_enable, + .set_invert = ti_ehrpwm_set_invert, +}; + +static const struct udevice_id ti_ehrpwm_ids[] = { + {.compatible = "ti,am3352-ehrpwm"}, + {.compatible = "ti,am33xx-ehrpwm"}, + {} +}; + +U_BOOT_DRIVER(ti_ehrpwm) = { + .name = "ti_ehrpwm", + .id = UCLASS_PWM, + .of_match = ti_ehrpwm_ids, + .ops = &ti_ehrpwm_ops, + .ofdata_to_platdata = ti_ehrpwm_ofdata_to_platdata, + .probe = ti_ehrpwm_probe, + .remove = ti_ehrpwm_remove, + .priv_auto_alloc_size = sizeof(struct ti_ehrpwm_priv), +};